Updating for litex uart IRQ move from zero to 2.

(And fixing IRQ conflicts that reveals.)
timvideos · Oct 30, 2017 · e1dc252 · e1dc252
1 parent 944d5f1
commit e1dc252
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Showing 3 changed files with 8 additions and 3 deletions.
diff --git a/targets/opsis/base.py b/targets/opsis/base.py
@@ -223,6 +223,11 @@ class BaseSoC(SoCSDRAM):
     )
     csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
 
+    interrupt_map = {
+        "uart": 2,
+    }
+    interrupt_map.update(SoCSDRAM.interrupt_map)
+
     mem_map = {
         "spiflash":     0x20000000,  # (default shadow @0xa0000000)
     }

diff --git a/targets/opsis/video.py b/targets/opsis/video.py
@@ -22,8 +22,8 @@ class VideoSoC(BaseSoC):
     csr_map_update(BaseSoC.csr_map, csr_peripherals)
 
     interrupt_map = {
-        "hdmi_in0": 3,
-        "hdmi_in1": 4,
+        "hdmi_in0": 4,
+        "hdmi_in1": 5,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 

diff --git a/third_party/litex b/third_party/litex