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Merge pull request #367 from mithro/litex-irq-fix
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LiteX uart is moving to IRQ 2
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mithro committed Oct 30, 2017
2 parents 944d5f1 + a9892e1 commit e653dd5
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Showing 9 changed files with 19 additions and 9 deletions.
2 changes: 1 addition & 1 deletion targets/arty/net.py
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ class NetSoC(BaseSoC):
csr_map_update(BaseSoC.csr_map, csr_peripherals)

interrupt_map = {
"ethmac": 2,
"ethmac": 3,
}
interrupt_map.update(BaseSoC.interrupt_map)

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2 changes: 1 addition & 1 deletion targets/atlys/net.py
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ class NetSoC(BaseSoC):
csr_map_update(BaseSoC.csr_map, csr_peripherals)

interrupt_map = {
"ethmac": 2,
"ethmac": 3,
}
interrupt_map.update(BaseSoC.interrupt_map)

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4 changes: 2 additions & 2 deletions targets/atlys/video.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,8 @@ class VideoSoC(BaseSoC):
csr_map_update(BaseSoC.csr_map, csr_peripherals)

interrupt_map = {
"hdmi_in0": 3,
"hdmi_in1": 4,
"hdmi_in0": 4,
"hdmi_in1": 5,
}
interrupt_map.update(BaseSoC.interrupt_map)

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5 changes: 5 additions & 0 deletions targets/nexys_video/base.py
Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,11 @@ class BaseSoC(SoCSDRAM):
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)

interrupt_map = {
"uart": 2,
}
interrupt_map.update(SoCSDRAM.interrupt_map)

mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
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2 changes: 1 addition & 1 deletion targets/nexys_video/net.py
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ class NetSoC(BaseSoC):
csr_map_update(BaseSoC.csr_map, csr_peripherals)

interrupt_map = {
"ethmac": 2,
"ethmac": 3,
}
interrupt_map.update(BaseSoC.interrupt_map)

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2 changes: 1 addition & 1 deletion targets/nexys_video/video.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ class VideoSoC(BaseSoC):
csr_map_update(BaseSoC.csr_map, csr_peripherals)

interrupt_map = {
"hdmi_in0": 3,
"hdmi_in0": 4,
}
interrupt_map.update(BaseSoC.interrupt_map)

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5 changes: 5 additions & 0 deletions targets/opsis/base.py
Original file line number Diff line number Diff line change
Expand Up @@ -223,6 +223,11 @@ class BaseSoC(SoCSDRAM):
)
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)

interrupt_map = {
"uart": 2,
}
interrupt_map.update(SoCSDRAM.interrupt_map)

mem_map = {
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}
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4 changes: 2 additions & 2 deletions targets/opsis/video.py
Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@ class VideoSoC(BaseSoC):
csr_map_update(BaseSoC.csr_map, csr_peripherals)

interrupt_map = {
"hdmi_in0": 3,
"hdmi_in1": 4,
"hdmi_in0": 4,
"hdmi_in1": 5,
}
interrupt_map.update(BaseSoC.interrupt_map)

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