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DDR Memory is currently broken on the Opsis #77

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mithro opened this issue Sep 26, 2015 · 13 comments
Open

DDR Memory is currently broken on the Opsis #77

mithro opened this issue Sep 26, 2015 · 13 comments
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@mithro
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board-opsis firmware-fpga firmware-softcpu hdmi2*** level-firmware type-bug

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@mithro
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mithro commented Sep 26, 2015 

$ git describe
v0.0.0-367-gb3f0b8f

BIOS> revision
c355d61e
BIOS> memtest
Memtest failed: 258598/532736 words incorrect
BIOS> memtest
Memtest failed: 249756/532736 words incorrect
BIOS> memtest
Memtest failed: 270214/532736 words incorrect
BIOS> memtest
Memtest failed: 249513/532736 words incorrect
BIOS>
@enjoy-digital
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Closing it since since working here with upstream versions hdmi2usb and all submodules.
Please re-open it if you still have issues.

Note: when failing, you will probably still be able to run the design with "romboot" command.

@mithro mithro assigned mithro and unassigned enjoy-digital Oct 14, 2015
@mithro mithro reopened this Oct 14, 2015
@mithro
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mithro commented Oct 14, 2015

It appears the board is booting fine now, but if I reboot and run a memtest I get errors.

tansell@tansell-z620-l2:~/foss/timvideos/hdmi2usb/HDMI2USB-misoc-firmware$ make connect-lm32
third_party/misoc/tools/flterm --port /dev/ttyACM0 --speed 115200
[FLTERM] Starting...

HDMI2USB>status
input0:  0x0
input1:  0x0
output0: 1280x720@60Hz from input0
output1: 1280x720@60Hz from input0
encoder: off
ddr: read: 1760Mbps  write:    0Mbps  all: 1760Mbps
HDMI2USB>reboot

MiSoC BIOS   http://m-labs.hk
(c) Copyright 2007-2014 Sebastien Bourdeauducq
Revision 8e860e3a built Oct 14 2015 16:49:37

BIOS CRC passed (c10d0f37)
Running on MiSoC rev. 8e860e3a (sysid:UN) at 50MHz
Initializing SDRAM...
Memtest failed: 271264/532736 words incorrect
Memory initialization failed
BIOS> memtest
Memtest failed: 219847/532736 words incorrect
BIOS> memtest
Memtest failed: 183676/532736 words incorrect
BIOS>

@enjoy-digital
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OK, can you try to stop output0 and output1 and do a reboot to see if you have the same behaviour?
We should maybe disable all DMA before doing a reboot.

@mithro
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mithro commented Oct 14, 2015

Still the same thing it appears;

HDMI2USB>status
input0:  0x0
input1:  0x0
output0: 1280x720@60Hz from input0
output1: 1280x720@60Hz from input0
encoder: off
ddr: read: 1757Mbps  write:    0Mbps  all: 1757Mbps
HDMI2USB>output0 off
Disabling output0
HDMI2USB>output1 off
Disabling output1
HDMI2USB>status
input0:  0x0
input1:  0x0
output0: off
output1: off
encoder: off
ddr: read:    0Mbps  write:    0Mbps  all:    0Mbps
HDMI2USB>reboot

MiSoC BIOS   http://m-labs.hk
(c) Copyright 2007-2014 Sebastien Bourdeauducq
Revision 8e860e3a built Oct 14 2015 16:49:37

BIOS CRC passed (c10d0f37)
Running on MiSoC rev. 8e860e3a (sysid:UN) at 50MHz
Initializing SDRAM...
Memtest failed: 527460/532736 words incorrect
Memory initialization failed
BIOS> memtest
Memtest failed: 524388/532736 words incorrect
BIOS> memtest
Memtest failed: 525000/532736 words incorrect
BIOS> memtest
Memtest failed: 524304/532736 words incorrect
BIOS>

@enjoy-digital
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Hmm OK, thanks for the test.

@mithro
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mithro commented Oct 14, 2015

There was a way to get more verbose information out of memtest, but I forget how?

@enjoy-digital
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For now, you can type "romboot" to restart the firmware

@sealne
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sealne commented Oct 18, 2015

running the opsis-fixes branch:

kd@azur:~/dev/HDMI2USB-misoc-firmware-mithro$ make connect-lm32
third_party/misoc/tools/flterm --port /dev/ttyACM0 --speed 115200
[FLTERM] Starting...

Command not found
BIOS> memtest
Memtest failed: 532480/532736 words incorrect
BIOS>
BIOS> romboot
Executing booted program.

HDMI2USB firmware http://timvideos.us/
Board's DNA: 00000000005c3875
Revision 8e860e3a built Oct 17 2015 17:32:40
HDMI2USB>

@mithro
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mithro commented Jan 10, 2016

I'm not seeing this issue any more.

@sealne Are you able to still reproduce this problem?

@sealne
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sealne commented Jan 11, 2016

i get no output now running memtest now

@mithro
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mithro commented Jan 26, 2016

@enjoy-digital This is back again now.....

@mithro
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mithro commented Jan 26, 2016 

BIOS> memtest
Memtest failed: 532480/532736 words incorrect
BIOS>

@mithro
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mithro commented Jan 26, 2016

Could there be a missing timing constraint somewhere. This means that some builds end up with a bad memory controller?

@mithro mithro mentioned this issue Feb 3, 2016
Closed
mithro added a commit that referenced this issue Aug 28, 2018
@mithro
Updating submodules.
9916c81 
 * edid-decode changed from dcc8b83 to b2da151
    * b2da151 - edid-decode: add --extract and --check options <Hans Verkuil>
    * e9ffafc - edid-decode: add options and new output formats <Hans Verkuil>
    * ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil>
    * 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil>
    * 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil>
    * eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil>
    * 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil>
    * 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil>
    * 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil>
    * bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil>
    * 7684918 - edid-decode: README: updates <Hans Verkuil>
    * 9e59ba9 - edid-decode: update links, add README <Hans Verkuil>
    * 0a454bc - makefile: also honor LDFLAGS <Adam Jackson>

 * litedram changed from 45da365 to 7a5ac75
    * 7a5ac75 - test/test_axi: improve test_axi2native <Florent Kermarrec>
    * d53832d - frontend/axi: split LiteDRAMAXI2Native (write path and read path) <Florent Kermarrec>
    * c846b8b - frontend/axi: add burst support (fixed/incr) <Florent Kermarrec>
    * 3fa77c8 - phy/s6ddrphy: use cwl only for DDR3 <Florent Kermarrec>
    * d9b5bb7 - frontend/bist: support axi with addressing in bytes <Florent Kermarrec>
    * 1370617 - frontend/axi: addressing in bytes not internal dwords <Florent Kermarrec>
    * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec>
    * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec>
    * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec>
    *   d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec>
    |\
    | *   cd330b4 - Merge pull request #28 from AlphamaxMedia/refactor-master <enjoy-digital>
    | |\
    | | * 818c678 - update module settings to reflect latest changes <bunnie>
    | | * c9b8db5 - i think there's a missing "self" in the params <bunnie>
    * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec>
    |/ /
    * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec>
    * | 5715734 - frontend: add initial AXI support <Florent Kermarrec>
    * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec>
    * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec>
    |/
    * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec>
    * 697eaaf - add board tuning parameters <bunnie>
    * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec>
    * 9401b92 - move sdram_init to litedram <Florent Kermarrec>
    * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec>
    * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec>
    * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec>
    * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec>
    * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec>
    * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec>
    * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec>
    * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec>
    *   db4ec67 - Merge pull request #24 from JohnSully/AutoPrecharge <enjoy-digital>
    |\
    | * 627cccd - Fix tCCD timing which watched the wrong command <>
    | * 16a852b - Revert "core/refresher: synchronize valid" <>
    | * a4be642 - Fix multiple timings ignored <>
    | *   771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <>
    | |\
    | |/
    |/|
    * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec>
    * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec>
    * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec>
    * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec>
    * |   eeb57ad - Merge pull request #23 from JohnSully/outoforder <enjoy-digital>
    |\ \
    | | * 3206985 - When auto-precharging assert track_close <>
    | | * 74279ea - Enable auto-precharge <>
    | |/
    | * 03a2ad6 - Ensure out of order is on a per-bank basis <>
    | * 86b3e2d - Add reorder flag to the crossbar <>
    | *   77c513d - Merge upstream.  UNTESTED <>
    | |\
    | |/
    |/|
    * | c28a754 - test: update <Florent Kermarrec>
    * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec>
    * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec>
    * |   26f3f01 - Merge pull request #21 from JohnSully/outoforder <enjoy-digital>
    |\ \
    * \ \   74c3c09 - Merge pull request #20 from bunnie/400mhz-pr <enjoy-digital>
    |\ \ \
    | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell>
    | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie>
    * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec>
    * | | |   5d74eb2 - Merge pull request #19 from JohnSully/timing <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <>
    | | | * ed4be0b - Add write bank to out of order interface <>
    | | |/
    | | * bfa1d6a - remove debug prints <>
    | | * 2fa2a6d - Initial implementation of out of order controller <>
    | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <>
    | |/
    | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <>
    | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <>
    |/
    * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec>
    * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec>
    * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec>
    * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec>
    * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec>
    * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec>
    * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec>
    * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec>
    * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec>
    * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec>
    * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec>
    * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec>
    * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec>
    *   d150e3b - Merge pull request #12 from JohnSully/master <enjoy-digital>
    |\
    | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <>
    | * d0fcfb1 - Auto-precharge now only fires when it needs to <>
    * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec>
    * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec>
    * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
    * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec>
    * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec>
    * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec>
    * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec>
    |/
    * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec>

 * liteeth changed from 33afda7 to 24b0d2b
    * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec>
    * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec>
    * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec>
    * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec>
    * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec>

 * litepcie changed from 8bc328f to a97a691
    * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec>
    * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec>
    * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec>
    * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec>
    * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec>
    * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec>
    * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec>
    * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec>
    * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec>
    * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec>
    * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec>

 * litesata changed from a559afb to 002cd25
    * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 73cb6fa - example_designs: update <Florent Kermarrec>
    * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec>
    * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec>
    *   8bdc28e - Merge pull request #14 from felixheld/crc <enjoy-digital>
    |\
    | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held>
    | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held>
    * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litescope changed from 9d5e605 to f26e36e
    *   f26e36e - Merge pull request #11 from xobs/add-trigger-depth <enjoy-digital>
    |\
    | * 71ffaa7 - add trigger depth option <bunnie>
    |/
    * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec>
    * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec>
    * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec>
    * 3efaefa - example_designs: typo <Florent Kermarrec>
    * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec>
    * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec>
    * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec>
    * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec>
    * a269e67 - software: add rising/falling edge support <Florent Kermarrec>
    * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec>
    * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec>
    * 26a8b89 - example_designs: update <Florent Kermarrec>
    * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec>

 * liteusb changed from 23d6a68 to e841c56
    * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litevideo changed from 9b4169d to 7b4240f
    * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cb8cf59 - Merge pull request #19 from bunnie/terc4-data <enjoy-digital>
    * c704235 - additional debugging on capture <bunnie>
    * eab7078 - add data decoding to Terc4 decoder <bunnie>
    * eb263a8 - add ability to invert the HPD input <bunnie>
    * 7189562 - fix a default edid that works better with rpis <bunnie>
    * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie>
    * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie>
    * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie>
    * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie>
    * 447726f - add RGB input mode support to hdmi in <bunnie>
    * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie>
    * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie>
    * 9b3c93e - move BUFR->BUFG <bunnie>
    * 166dc57 - fix typo on naming <bunnie>
    * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie>
    * 784cc8c - changes needed for a basic genlock <bunnie>

 * litex changed from v0.1-319-gb7f7c8d1 to v0.1-423-g7a14b75c
    *   7a14b75c - Merge pull request #93 from phlipped/master <Tim Ansell>
    |\
    | * 8b51c445 - Fix URL for liteUSB <phlipped>
    |/
    *   0074bb88 - Merge pull request #91 from cr1901/ignore-fix <Tim Ansell>
    |\
    | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones>
    * |   ff908e40 - Merge pull request #92 from cr1901/l2-gate <Tim Ansell>
    |\ \
    | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones>
    | |/
    * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec>
    * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec>
    * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec>
    * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec>
    * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec>
    * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec>
    * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec>
    * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec>
    * | 2eeccc50 - vexriscv: update <Florent Kermarrec>
    * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec>
    |/
    * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec>
    * 4225c3b8 - update Vexriscv <Florent Kermarrec>
    * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec>
    * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec>
    * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec>
    * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec>
    * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec>
    * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec>
    * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec>
    *   e07ca057 - Merge pull request #86 from pgielda/patch-1 <enjoy-digital>
    |\
    | * 3c7890cd - Fix generating csr.csv file <Peter Gielda>
    |/
    * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec>
    * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec>
    * 580efecc - picorv32: add reset signal <Florent Kermarrec>
    * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec>
    * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec>
    * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec>
    * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec>
    *   380f8b96 - Merge pull request #81 from xobs/vexriscv-to-wishbone <enjoy-digital>
    |\
    | * fb145dac - tools: remove vexriscv_debug <Sean Cross>
    | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross>
    | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross>
    |/
    * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec>
    * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec>
    * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec>
    * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec>
    * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec>
    * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec>
    * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec>
    * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec>
    * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec>
    *   55dd58b0 - Merge pull request #80 from xobs/fix-vexriscv-csr-read <enjoy-digital>
    |\
    | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross>
    * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec>
    * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec>
    * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec>
    * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec>
    * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec>
    |/
    * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec>
    * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec>
    *   b062d4dd - Merge pull request #79 from xobs/fix-vexriscv-data-read <enjoy-digital>
    |\
    | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross>
    |/
    *   e35be26e - Merge pull request #78 from xobs/vexriscv_debug_bridge <enjoy-digital>
    |\
    | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross>
    | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross>
    |/
    * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec>
    * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec>
    *   6068f6ce - Merge pull request #77 from xobs/debug-vexriscv-enjoy <enjoy-digital>
    |\
    | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross>
    | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross>
    | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross>
    | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross>
    * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec>
    * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec>
    |/
    * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec>
    * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec>
    * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec>
    * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec>
    * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec>
    * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec>
    * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec>
    * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec>
    * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec>
    * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec>
    * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec>
    * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec>
    * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec>
    *   78639fa9 - Merge pull request #75 from xobs/bios-windows-build <enjoy-digital>
    |\
    | * 74449929 - soc: bios: fix windows build <Sean Cross>
    |/
    * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec>
    * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec>
    *   c534250c - Merge pull request #72 from bunnie/fix_riscv_boothelper <enjoy-digital>
    |\
    | * 7353197e - fix the vexriscv boot helper <bunnie>
    |/
    *   5ab4282e - Merge pull request #71 from DeanoC/master <enjoy-digital>
    |\
    | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver>
    |/
    * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec>
    * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec>
    * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec>
    * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990>
    * f60da4a5 - add VexRiscv submodule <Florent Kermarrec>
    * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec>
    * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec>
    * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec>
    * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec>
    * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec>
    * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec>
    * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec>

 * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5
    * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera>
    * 2d37c78 - add indexed part select support <Robin Ole Heinemann>
    * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (#111) <William D. Jones>
    * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark>
    * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark>
    * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark>
    * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark>
    * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark>
    * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq>
    * 47f4c59 - typo <Sebastien Bourdeauducq>
    * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq>
    * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq>
    * cb171af - platform: support adding connectors <Sebastien Bourdeauducq>
    * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (#88) <William D. Jones>
    * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq>
    * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec>
    * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty>
    * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq>
    * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq>
    * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq>
    * df0ce4a - Update version in setup.py. <whitequark>
    * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison>
    * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison>
    * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison>
    * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison>
    * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison>
    * ede1c9e - Add _connectors to constructor <Caleb Jamison>
    * 20d28d4 - Removed extra field from _connector list <Caleb Jamison>
    * 02e80df - Add chipkit io to _connector list <Caleb Jamison>
    * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison>
    * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison>
    * 04a9914 - Arty A7 platform <Caleb Jamison>
    * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński>
    * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens>
    * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens>
    * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq>
    * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq>
    * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq>
    * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens>
    * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens>
    * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec>
    * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark>
    * e66f2df - Fix documentation link in README. <whitequark>
    * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark>
    * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones>
    * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones>
    * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec>
    * 9bc084a - Update .gitignore. <whitequark>
    * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark>
    * 02bccef - Fix breakage introduced in 2220222. <whitequark>
    * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark>
    * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark>
    * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens>
    * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens>
    * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq>
    * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (#96) <Adam Greig>
    * c14a1e4 - Add MyStorm BlackIce I and II platforms (#95) <Adam Greig>
    * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq>
    * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq>

Full submodule status
--
 b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 7a5ac75e2295dcf15f83df966244f30154a8f662 litedram (remotes/origin/HEAD)
 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD)
 a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD)
 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD)
 f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD)
 e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD)
 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD)
 7a14b75cd676e9328063abc1fcdc6fcd4fc6c5ef litex (v0.1-423-g7a14b75c)
 a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)
mithro pushed a commit that referenced this issue Jul 2, 2019
@mateusz-holenko
Updating submodules.
403f459 
 * edid-decode changed from 6def7bc to 15df4ae
    * 15df4ae - Makefile: add CPPFLAGS <Hans Verkuil>
    * dc763d7 - Update email addresses <Hans Verkuil>
    * 726576d - edid-decode: add CTA-861.4/5 support <Hans Verkuil>

 * flash_proxies changed from a628956 to 1c21ee4
    * 1c21ee4 - README: update <Robert Jördens>

 * litedram changed from d89b171 to 67de3ce
    *   67de3ce - Merge pull request #85 from antmicro/fix_databits <enjoy-digital>
    |\
    | * 24851c9 - PhySettings: set missing databits parameter for S6QuarterRateDDRPHY <Mateusz Holenko>
    * | fef5303 - test: clean test_downconverter/test_upconverter (thanks sb0) <Florent Kermarrec>
    |/
    *   7fbe0b7 - Merge pull request #84 from open-design/is42s16320 <enjoy-digital>
    |\
    | * 5c66547 - modules: SDRAM: add IS42S16320 support <Antony Pavlov>
    |/
    * 8e2df17 - modules: fix tRFC change on MT16KTF1G64HZ <Florent Kermarrec>
    * bc88cfa - modules: allow tRFC to be defined in ck or ns, fix some DDR3/DDR4 definitions (thanks @ambrop72 for the review) <Florent Kermarrec>
    * fbd7ae3 - modules: make IS43TR16128B consistent with others SDRAMModules <Florent Kermarrec>
    *   02448a3 - Merge pull request #83 from ambrop72/IS43TR16128B_125K <enjoy-digital>
    |\
    | * d108970 - modules/ddr3: add IS43TR16128B_125K <Ambroz Bizjak>
    |/
    *   da68e21 - Merge pull request #82 from gsomlo/gls-expose-csr <enjoy-digital>
    |\
    | * 65451f4 - examples/litedram_gen: allow direct access to CSR (I/O) registers <Gabriel L. Somlo>
    |/
    * 50e1d47 - PhySettings: add databits to allow SoC to compute memory size more easily <Florent Kermarrec>
    * b93412b - examples: remove verilog simulation <Florent Kermarrec>
    * a7e46bb - example/litedram_gen: reserve_nmi_interrupt no longer exists <Florent Kermarrec>
    *   094fc2e - Merge pull request #79 from gsomlo/gls-ulong-addr <enjoy-digital>
    |\
    | * 54d3312 - sdram_init: use "unsigned long" for address values <Gabriel L. Somlo>
    |/
    * 3caaa2e - common/tXXDController: revert Yosys workarounds <Florent Kermarrec>
    * 44bbb93 - phy: add copyrights <Florent Kermarrec>
    * 6ddc2c8 - README: update <Florent Kermarrec>
    * 9190a76 - travis: simplify and add RISC-V toolchain to run examples <Florent Kermarrec>
    * e824288 - frontend/axi: move AXIBurst2Beat to LiteX <Florent Kermarrec>
    * be269da - frontend/axi: use definitions from LiteX <Florent Kermarrec>
    * e81b5a1 - sdram_init: set __attribute__((unused)) on command_px to avoid compilation warning <Florent Kermarrec>
    * c4161cf - examples: update sim <Florent Kermarrec>
    * 201a0e2 - test/test_examples: add nexys4ddr <Florent Kermarrec>
    * 69afaf5 - common: add separators, reorganize a bit <Florent Kermarrec>
    * 0bc241c - phy/ecp5ddrphy: use inline comments on ECP5DDRPHYInit <Florent Kermarrec>
    * c65ff97 - phy/ecp5ddrphy: simplify ECP5DDRPHYInit, integrate it in the PHY, add burstdet registers <Florent Kermarrec>
    * 4274db8 - common/TXXDcontroller: fix for compatibility with Yosys and vendor tools <Florent Kermarrec>
    * a74d5c9 - common/TXXDcontroller: set ready default value to 1 with self.comb instead of reset value <Florent Kermarrec>
    *   cec35f3 - Merge pull request #77 from daveshah1/ecp5_75MHz <enjoy-digital>
    |\
    | * fa26dcd - ecp5ddrphy: Shift read position forwards to fix higher frequencies <David Shah>
    |/
    *   6715c1b - Merge pull request #76 from daveshah1/trellis_io <enjoy-digital>
    |\
    | * 691d930 - ecp5ddrphy: Use triples for inputs to fix build with TRELLIS_IOs <David Shah>
    |/
    * 9057f51 - phy: add ECP5 imports <Florent Kermarrec>
    * f660618 - phy: add initial ECP5DDRPHY <Florent Kermarrec>
    * 640194a - examples: add nexys4ddr_config <Florent Kermarrec>
    * 0ac1af3 - examples/litedram_gen: add DDR2 support <Florent Kermarrec>
    * f4184ec - example/litedram_gen: update, add descriptions of config parameters <Florent Kermarrec>
    * 79806aa - modules/ddr3: add MT41K64M16 <Florent Kermarrec>
    * ea6b841 - phy/s7ddrphy and usddrphy: add cmd_latency parameter <Florent Kermarrec>
    * fd3e9af - phy/s7ddrphy: fix cmd delays <Florent Kermarrec>
    * f61c8d9 - phy/s7ddrphy: make clk/cmd odelaye2s configurable <Florent Kermarrec>
    * e0224f4 - phy/usddrphy: make clk/cmd odelaye3s configurable <Florent Kermarrec>

 * liteeth changed from 77fa4bf to 2424e62
    * 2424e62 - software: also include generated/mem.h <Florent Kermarrec>
    * e88fc50 - software: remote ethmac_mem.h dependency (no longer exists in LiteX) <Florent Kermarrec>
    * b318300 - phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked <Florent Kermarrec>
    * e6c35cd - phy/ku_1000basex: incease pll_reset <Florent Kermarrec>
    * 816f592 - phy: add initial ECP5RGMII PHY <Florent Kermarrec>
    * b4c1cfe - core/icmp: fix reply checksum when request checksum >= 0xf800 <Florent Kermarrec>

 * litepcie changed from 3804c49 to de6cd01
    * de6cd01 - frontend/dma: ensure we finish LitePCIeDMAWriter transaction when DMA is disabled. <Florent Kermarrec>
    * 260c562 - frontend/wishbone: cleanup qword_aligned support <Florent Kermarrec>
    * 89b3920 - README: update <Florent Kermarrec>
    * 22310cc - phy: add initial Cyclone5 support <Florent Kermarrec>
    * 9cdb982 - phy/s7pciephy: rename external_phy to external_hard_ip <Florent Kermarrec>
    * 3b6cffd - frontend/wishbone: add qword_aligned parameter <Florent Kermarrec>
    * d191b1e - core: add endianness support <Florent Kermarrec>
    * 4df720a - examples/targets/dma: remove typo (dma connection is done internally in loopback mode) <Florent Kermarrec>
    * 14d852e - examples/targets/dma: remove soft reset, simplify crg, minor cleanups <Florent Kermarrec>
    * 64857af - phy/s7pciephy: improve presentation <Florent Kermarrec>
    * 55fa0d4 - phy/s7pciephy: remove pcie clk presence detection. <Florent Kermarrec>
    * f042273 - phy/s7pciephy: allow using external sources for the PHY. <Florent Kermarrec>
    * bd5d4dc - phy/s7pciephy: remove unnecessary reset on pcie clock domain <Florent Kermarrec>
    * ccfb201 - frontend/dma: update loop_status when request is sent <Florent Kermarrec>

 * litesata changed from b78a731 to 6fe4cce
    * 6fe4cce - examples/targets/bist: simplify analyzer <Florent Kermarrec>
    * 846bd62 - phy/a7sataphy: rework tx/rx_startup_fsm using liteiclink code <Florent Kermarrec>
    * 5e02ac9 - phy/a7sataphy: use proper transceiver name <Florent Kermarrec>
    * e63c8aa - examples/test/test_analyzer: use shorter import <Florent Kermarrec>
    * 319dd72 - examples/targets/bist: update <Florent Kermarrec>
    * df27cdf - examples/targets: add bist_nexys_video (still wip) <Florent Kermarrec>
    *   2ba5508 - Merge pull request #15 from enjoy-digital/artix7 <enjoy-digital>
    |\
    | * 0b254b0 - examples/make: remove platform option <Florent Kermarrec>
    | * e0fc55c - examples/targets/bist: revert kc705/genesys2 bist example <Florent Kermarrec>
    | * cabc908 - example: add led blinking on refclk, add startup fsm to analyzer <Florent Kermarrec>
    | * d16b495 - examples: add more debug, rx/tx leds not blinking (no clock? bad init?) <Florent Kermarrec>
    | * 1519dc3 - targets/bist: use 100 MHz clock, fix reset polarity <Florent Kermarrec>
    | * 1fe543f - phy/a7sataphy: integrate GTPQuadPLL <Florent Kermarrec>
    | * ca47e05 - examples/targets/bist: start artix7 testing with sata_gen1 <Florent Kermarrec>
    | * 1fc848e - examples: add nexys_video support <Florent Kermarrec>
    | * 9152729 - phy/a7sataphy: update parameters from wizard <Florent Kermarrec>
    | * ef5d0b9 - phy: add initial a7sataphy <Florent Kermarrec>
    | * 12b5085 - phy/k7sataphy: remove drp interface (not used) <Florent Kermarrec>
    | * 246487c - phy/k7sataphy: improve readibility <Florent Kermarrec>
    | * 41f4446 - phy/k7sataphy: make GTXE2_CHANNEL instance similar to gtx_7series in liteiclink <Florent Kermarrec>
    | * 27df062 - phy: replace trx_dw with data_width <Florent Kermarrec>
    | * d52c7b8 - phy/k7sataphy: remove ones <Florent Kermarrec>
    | * 1d1da98 - phy/k7sataphy: refactor gtxe2_channel instance <Florent Kermarrec>
    | * 10d6376 - phy: move k7 phy to a single k7sataphy file <Florent Kermarrec>
    * 7299fef - example/make.py: create the build directory when building the core if not existing <Florent Kermarrec>

 * litescope changed from c1d8bdf to 2474ce9
    * 2474ce9 - software/dump/common: change variable name for values2x loop (thanks keesj) <Florent Kermarrec>
    * 7f20aa4 - examples/make/build-core: create build directory if not existing <Florent Kermarrec>

 * litex changed from af52842f to 113f7f40
    *   113f7f40 - Merge pull request #199 from ambrop72/no-ethmac-fix <enjoy-digital>
    |\
    | * ca70ea91 - bios: Fix build when ethphy is present but ethmac is not. <Ambroz Bizjak>
    |/
    * ab1f5804 - test/test_axi: remove litex.gen.sim import (was only useful for debug) <Florent Kermarrec>
    * 5318bcd3 - setup.py: add migen to install_requires <Florent Kermarrec>
    *   33d7cc5f - Merge pull request #198 from TomKeddie/tomk_20190610_artyspi <enjoy-digital>
    |\
    | * 5346c368 - boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2 <Tom Keddie>
    * | 38a2d89a - test/test_code8b10b: add test_coding <Florent Kermarrec>
    * | 8fdd5220 - test/test_prbs: add PRBSGenerator/Checker tests <Florent Kermarrec>
    * | 243d7c76 - soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker <Florent Kermarrec>
    * | cfa952b0 - tools/litex_term: exit on 2 consecutive CTRL-C <Florent Kermarrec>
    * | 1c34b4a0 - cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 79665873 - doc: add litex-hub logo <Florent Kermarrec>
    * | 442d7358 - doc: redesign new logo <Florent Kermarrec>
    * | 59118627 - doc: add new logo <Florent Kermarrec>
    * | 850b311d - cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 755a2660 - build/sim: allow configuring verilator optimization level <Florent Kermarrec>
    * | 4b6ad8aa - build/sim: allow defining start/end cycles for tracing <Florent Kermarrec>
    * | ecb60f6e - build/sim: use -O0 for verilator compilation <Florent Kermarrec>
    * | c64129dc - soc/integration/soc_core: list rocket as supported CPU <Florent Kermarrec>
    * | ca4e7811 - software/bios: change prompt to "litex" in green. <Florent Kermarrec>
    * | 8d0f008a - integration/soc_core: improve readibility (add separators/comments) <Florent Kermarrec>
    * | 55ebcc00 - test/test_targets: add de10lite <Florent Kermarrec>
    * |   e545b15f - Merge pull request #196 from msloniewski/de10lite_support <enjoy-digital>
    |\ \
    | * | 04ce4790 - boards/targets: add target for de10lite platform <msloniewski>
    | * | f2a740d5 - boards/platforms: add de10lite Terasic platform support <msloniewski>
    | * | a826aaca - build/altera: Add possibility to turn off generation of .rbf file <msloniewski>
    * | |   77805a5e - Merge pull request #195 from antmicro/extend_generated_headers <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 93b61a65 - integration/builder: generate flash_boot address to csv <Mateusz Holenko>
    | * | d0b019b1 - integration/builder: generate shadow_base address to mem.h and csv <Mateusz Holenko>
    |/ /
    * |   cb2d4372 - Merge pull request #193 from gsomlo/gls-memcpy-fix <enjoy-digital>
    |\ \
    | * | f88b85a3 - software/libbase: memcpy: simple, arch-width agnostic implementation <Gabriel L. Somlo>
    |/ /
    * |   42e9d097 - Merge pull request #192 from sutajiokousagi/pr_c99_types <Tim Ansell>
    |\ \
    | * | ab0b2cac - fix signed char type to be explicitly signed <bunnie>
    * | |   b0d35a49 - Merge pull request #191 from sergachev/master <Tim Ansell>
    |\ \ \
    | * | | db890736 - fix csr_name in add_csr() <Ilia Sergachev>
    | * | | 40cbe3a9 - fix interrupt_name <Ilia Sergachev>
    |/ / /
    * | | b300c321 - test/test_targets: add de2_115, de1soc <Florent Kermarrec>
    * | | 220e2bdc - boards/platform/arty: add Arty A7-100 variant <Florent Kermarrec>
    * | |   8e6ecfb9 - Merge pull request #189 from open-design/terasic-boards <enjoy-digital>
    |\ \ \
    | * | | 6cf1a814 - boards: add Terasic DE2-115 initial support <Antony Pavlov>
    | * | | 03725991 - boards: add Terasic DE1-SoC Board support <Antony Pavlov>
    * | | |   9682189b - Merge pull request #190 from sutajiokousagi/pr_c99_types <Tim Ansell>
    |\ \ \ \
    | |/ / /
    |/| / /
    | |/ /
    | * | 200d413d - update stdint.h to include c99 types <bunnie>
    |/ /
    * |   a48858f8 - Merge pull request #188 from gsomlo/gls-csr-cleanup <enjoy-digital>
    |\ \
    | * | 273a3ea1 - soc/integration/cpu_interface: improve code legibility <Gabriel L. Somlo>
    |/ /
    * | 08a811b1 - soc/interconnect/gearbox: add msb_first/lsb_first order <Florent Kermarrec>
    * | 675f7830 - boards/targets/arty: generate 25MHz ethernet clock with S7PLL <Florent Kermarrec>
    * |   d7b00c8c - Merge pull request #187 from open-design/indent <Tim Ansell>
    |\ \
    | * | 26e6355f - litex/boards/targets: don't use tab for indentation <Antony Pavlov>
    |/ /
    * | 51095112 - soc/interconnect/axi: add round/robin arbitration between writes/reads <Florent Kermarrec>
    * | 0fb6342f - travis: update RISC-V toolchain <Florent Kermarrec>
    * | 961101d8 - bios/irc: remove compilation workaround <Florent Kermarrec>
    * | cd543b29 - README: update RISC-V toolchain <Florent Kermarrec>
    * | 7e837bf1 - .gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog <Florent Kermarrec>
    * | 712977a0 - software/bios/isr.c: workaround compilation issue (need to be fixed) <Florent Kermarrec>
    * | 28ba8b32 - soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now) <Florent Kermarrec>
    * | cf369c43 - boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it) <Florent Kermarrec>
    * |   aa640f29 - Merge pull request #186 from gsomlo/gls-rocket <enjoy-digital>
    |\ \
    | * | 019fd940 - fixup: generated-verilog submodule for experimental Rocket support <Gabriel L. Somlo>
    | * | 1a530cf2 - soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) <Gabriel L. Somlo>
    |/ /
    * |   3de49118 - Merge pull request #185 from gsomlo/gls-sim-sdram <enjoy-digital>
    |\ \
    | |/
    |/|
    | * e90caa86 - tools/litex_sim: restore functionality of '--with-sdram' option <Gabriel L. Somlo>
    |/
    *   3a72688b - Merge pull request #183 from xobs/usb-to-0x43 <enjoy-digital>
    |\
    | * 014c9505 - remote: usb: print "access denied" error <Sean Cross>
    | * faf6554c - remote: usb: use 0x43/0xc3 for packet header <Sean Cross>
    |/
    * 10670e22 - soc/cores/minerva: update to latest <Florent Kermarrec>
    *   a3134f13 - Merge pull request #182 from gsomlo/gls-nexys4-eth-fixup <enjoy-digital>
    |\
    | * 5707bdc0 - boards/nexys4ddr: ethernet support fix-up <Gabriel L. Somlo>
    |/
    *   0a8699f1 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | * 1ea22d49 - software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva <Florent Kermarrec>
    * | 526ba1b1 - soc_core: remove csr_expose and add add_csr_master method <Florent Kermarrec>
    |/
    * f2570701 - software/bios/boot: remove specific linux commands (not needed with device tree) <Florent Kermarrec>
    * 938d00c2 - boards/targets/de0nano: reduce to 50MHz sys_clk, simplify CRG <Florent Kermarrec>
    * 11838bae - platforms/de0nano: change serial pins (put then next to the GND pin) <Florent Kermarrec>
    * eb6fa458 - cpu/vexriscv/core: update <Florent Kermarrec>
    * 0cad80e9 - cpu/vexriscv: update submodule (new linux variant) <Florent Kermarrec>
    * 5f6e7874 - boards/nexys4ddr: add ethernet support (RMII 100Mbps) <Florent Kermarrec>
    * 0ba1cb87 - boards/targets/netv2: +x <Florent Kermarrec>
    * 2f2b9b31 - soc/cores: remove cordic <Florent Kermarrec>
    * 6e4ac1c4 - LICENSE: clarify <Florent Kermarrec>
    * 67159349 - soc/interconnect: remove axi_lite <Florent Kermarrec>
    * 745d83a3 - boards: add initial NeTV2 support (clocks, leds, dram, ethernet) <Florent Kermarrec>
    * a49d170a - soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy <Florent Kermarrec>
    * 7445b9e2 - soc/integration/soc_core: allow user to defined internal csr/interrupts <Florent Kermarrec>
    * f333abcf - boards/targets: use new add_csr method <Florent Kermarrec>
    * d76a2c7d - tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method) <Florent Kermarrec>
    * b6be534c - soc/integration/soc_core: rework csr assignation/reservation <Florent Kermarrec>
    * 3f09af6d - boards/targets: declare ethmac interrupt with new add_interrupt method <Florent Kermarrec>
    *   2abb3e80 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   c11eb4b5 - Merge pull request #179 from gsomlo/gls-xtra-addrlen <enjoy-digital>
    | |\
    | | * c264a009 - soc/integration/cpu_interface: more arch-specific address size fixes <Gabriel L. Somlo>
    | |/
    * | 47dc8758 - integration/soc_core: rework interrupt assignation/reservation <Florent Kermarrec>
    * | 3ee9ce05 - test/test_targets: fix test_ulx3s name <Florent Kermarrec>
    * | 435cdad0 - boards/targets: fix ulx3s/versa_ecp5 build <Florent Kermarrec>
    * | 8caa38bc - cpu: add `reserved_interrupts` property <Mateusz Holenko>
    * | ff517915 - boards/targets: make sys_clk_freq a parameter <Florent Kermarrec>
    |/
    * a8cbe4ad - boards/targets/minispartan6: for now revert experimental s6pll clocking <Florent Kermarrec>
    * 6fcbf10e - boards/plarforms/minispartan6: default to xc6slx25 <Florent Kermarrec>
    * b7e37133 - bios/boot/ update linux memory mapping <Florent Kermarrec>
    * 190ff89a - tools/litex_term: add json support to load images to memory, allow passing speed as float <Florent Kermarrec>
    *   a50aff2c - Merge pull request #178 from daveshah1/vexriscv_linux_yosys <enjoy-digital>
    |\
    | * a048ba47 - vexriscv: Fix some floating signals <David Shah>
    |/
    * fcd518b5 - bios/boot: add specific flash_boot for linux with vexriscv <Florent Kermarrec>
    * 1ba1ad9a - bios/boot: rename MM_RAM to EMULATOR_RAM <Florent Kermarrec>
    * fbb24720 - soc/get_mem_data: add direct support for regions <Florent Kermarrec>
    * 0714816f - soc/interconnect/axi: add AXI2AXILite converter and use it in  AXI2Wishbone <Florent Kermarrec>
    * c6d0d234 - soc/interconnect/axi: add AXI Lite definition <Florent Kermarrec>
    * 9fab4752 - soc/interconnect/axi: add comment on axi signas that are present but not used <Florent Kermarrec>
    * 59890763 - cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant <Florent Kermarrec>
    * 21bf1038 - bios/boot: add liftoff banner just before booting <Florent Kermarrec>
    * 8f4685b3 - bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config <Florent Kermarrec>
    * 6cf1ff09 - soc/interconnect/axi: connect axi.ar/aw when selecting write or read <Florent Kermarrec>
    * 6affc56a - soc/interconnect/axi: wishbone address shift is not always 2, make it generic <Florent Kermarrec>
    * 698bc882 - soc/interconnect/wishbone: allow setting adr_width (default to 30) <Florent Kermarrec>
    * 4dccb8a9 - soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent <Florent Kermarrec>
    * 9f8f0eb1 - build/sim: update tapcfg <Florent Kermarrec>
    *   2515c7b0 - Merge pull request #176 from gsomlo/gls-ulong-addr <enjoy-digital>
    |\
    | * 5c2b8685 - software: use "unsigned long" for address values, also 8-byte alignment <Gabriel L. Somlo>
    |/
    * 74d37465 - test/test_targets: comment bad variant tests for now <Florent Kermarrec>
    * 5c1d9805 - soc/interconnect/axi: add burst support to AXI2Wishbone <Florent Kermarrec>
    * 6de27135 - soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize <Florent Kermarrec>
    * 305b8879 - integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k) <Florent Kermarrec>
    * 4e50f36b - build/tools: add deprecated_warning <Florent Kermarrec>
    * b40d1b73 - cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang) <Florent Kermarrec>
    * dbb71af1 - cpu: use property methods to return name, endianness, gcc triple/flags, linker output format <Florent Kermarrec>
    * d828c3a5 - cpu: integrate nmigen version of Minerva, add submodule <Florent Kermarrec>
    * 2c3c6bdf - Updating documents from LiteX BuildEnv Wiki <Florent Kermarrec>
    * bf27869a - fix vexriscv build <Kurt Kiefer>
    *   2d5bae3d - Merge pull request #175 from mithro/cpu-docs <enjoy-digital>
    |\
    | * 5cbc5bc1 - Adding testing of cpu variants. <Tim 'mithro' Ansell>
    | * 71a83731 - Work with no `cpu_variant` provided. <Tim 'mithro' Ansell>
    | * 65650919 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell>
    | * a43de819 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell>
    | * 39c579ba - Standardize the `cpu_variant` strings. <Tim 'mithro' Ansell>
    | * e42de8fe - docs: Adding script to pull useful docs from LiteX BuildEnv's wiki. <Tim 'mithro' Ansell>
    * | 3a2e2836 - .gitmodules: use our VexRiscv-verilog <Florent Kermarrec>
    |/
    * 78c09125 - soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes <Florent Kermarrec>
    * 0175f86c - soc/integration/soc_core: fix get_mem_data for json files <Florent Kermarrec>
    * 4443b507 - soc/integration/soc_core: add integrated_sram_init <Florent Kermarrec>
    * f27084c6 - soc/integration/cpu_interface: fix banner in get_mem_header <Florent Kermarrec>
    *   5ec99d94 - Merge pull request #173 from gsomlo/gls-git-revision <enjoy-digital>
    |\
    | * d21cba2f - build: handle exceptional case when litex/migen not deployed as git repo <Gabriel L. Somlo>
    |/
    * 27fbb814 - tools/remote/csr_builder: allow comments in csv file and cleanup <Florent Kermarrec>
    * e8f3c491 - software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding <Florent Kermarrec>
    * 44e0cdda - software/libnet/microudp: speed-up ARP by changing timeout/tries <Florent Kermarrec>
    * 3ee78a5b - build/tools: fix typo <Florent Kermarrec>
    * f0fe9f3c - setup.py: add short names for tools <Florent Kermarrec>
    * 9ded2eb2 - tools/litex_term: change TERM prompt to LXTERM <Florent Kermarrec>
    * 475deb51 - build: add migen and litex git revision to generated file <Florent Kermarrec>
    * 8b5cf295 - build/tools: git_revision is not doing what we want, return "--------" for now <Florent Kermarrec>
    * 228f2867 - litex_setup: revert default install behaviour but add --user support <Florent Kermarrec>
    *   9fbbf928 - Merge pull request #171 from keesj/develop_as_user <enjoy-digital>
    |\
    | * 24bdb648 - Install development packages in the user directory <Kees Jongenburger>
    * | 0f60ec35 - tools/litex_server: fix comms import <Florent Kermarrec>
    * | 68f12495 - soc/integration: also add sha-1/date to generated software files <Florent Kermarrec>
    * | 42574122 - build: add sha-1/date to generated verilog, change git_version to git_revision <Florent Kermarrec>
    |/
    * f7c0b118 - test/test_targets: cover all platforms <Florent Kermarrec>
    * 818dfae1 - boards/platforms/ulx3s: fix default clock <Florent Kermarrec>
    * 17b6164c - boards/platforms/sp605: apply same simplifications than on others platforms <Florent Kermarrec>
    * 24bf0293 - boards/platforms: add SP605 <Michael Betz>
    * 10cf0fde - cores/cpu/vexriscv: fix wrong revert <Florent Kermarrec>
    * d2ad1441 - targets/ac701: cleanup and make it similar to others targets. <Florent Kermarrec>
    * a24bf72f - targets/xilinx: remove keep attribute on clock going to idelayctrl <Florent Kermarrec>
    * ea8dbff8 - boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms <Florent Kermarrec>
    * 0122982e - boards/platforms/kc705: provide only one default programmer as others platforms <Florent Kermarrec>
    * 89a59026 - boards: Xilinx ac701 dev board support <Vamsi K Vytla>
    * 88b882c7 - build/xilinx/ise.py: write .v file for post synthesis sim <Michael Betz>
    * 7396ebbb - build/xilinx/programmer: cleanup XC3SProg position parameter <Florent Kermarrec>
    * f579cbc6 - build/xilinx/programmer: add position parameter to XC3SProg <Michael Betz>
    * fb4f8818 - .gitignore: ignore tilde files <Vamsi K Vytla>
    * 535d8672 - targets/minispartan6: use S6PLL in CRG <Florent Kermarrec>
    * 40342404 - cores/clock: add divclk_divide_range on S6PLL/S6DCM <Florent Kermarrec>
    * 0d282f38 - cores/clock: use common XilinxClocking class for all Xilinx clocking modules <Florent Kermarrec>
    * 83699ea0 - cores/clock: add initial Spartan6 PLL/DCM support <Michael Betz>
    * eff141da - build: add git version (sha-1) used to create the scripts <Florent Kermarrec>
    * cc141a64 - build: scripts are generated by LiteX <Florent Kermarrec>
    * 115c842e - build/xilinx/vivado: cleanup pull request #170 <Florent Kermarrec>
    *   3b24b8d5 - Merge pull request #170 from ldoolitt/master <enjoy-digital>
    |\
    | * fda18fd6 - build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path <Larry Doolittle>
    |/
    * 7d278854 - global: switch to VexRiscv as the default CPU <Florent Kermarrec>
    * 28d80bd6 - ci: fix test_targets/test_simple <Florent Kermarrec>
    * b7f53fb9 - test: remove waveforms generation <Florent Kermarrec>
    * e98ac680 - travis: simplify, enable and add RISC-V toolchain to build targets <Florent Kermarrec>
    * 8c789970 - boards/platforms: add separators, cleanup imports <Florent Kermarrec>
    * cb8c26d1 - boards/platforms: provide only one default programmer per platform. <Florent Kermarrec>
    * e1d202df - boards/platforms/kc705: only keep Vivado support <Florent Kermarrec>
    * 53c7be6e - boards: always define timing constraints the same way (1e9/freq_mhz) <Florent Kermarrec>
    * 02ffbed5 - boards/targets/ulx3s: allow running test_targets on it <Florent Kermarrec>
    * 5a1925df - boards/targets: add keep attribute directly in crg <Florent Kermarrec>
    *   67a79d7c - Merge pull request #167 from xobs/network-flag-check <enjoy-digital>
    |\
    | * f71b8d4f - litex_server: check socket flags exist before using them <Sean Cross>
    |/
    * 9ee6c35b - tools: move from litex.soc.tools to litex.tools and fix usb.core import <Florent Kermarrec>
    *   49fd93ae - Merge pull request #165 from xobs/vexriscv-cpu-reset-address <enjoy-digital>
    |\
    | *   c780fb22 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Sean Cross>
    | |\
    | * | e2cf45b8 - cpu: vexriscv: allow cpu_reset_address to be overridden <Sean Cross>
    * | |   ca6065a6 - Merge pull request #164 from xobs/litex-usb-server <enjoy-digital>
    |\ \ \
    | * | | c6918364 - utils: litex_server: add usb support <Sean Cross>
    | * | | 9dd59d63 - tools: remote: add usb communications protocol <Sean Cross>
    * | | | 9cbed91b - soc/interconnect/axi: add AXIBurst2Beat <Florent Kermarrec>
    * | | | 5a8115d9 - soc/interconnect/avalon: add description <Florent Kermarrec>
    | |_|/
    |/| |
    * | | fa956086 - soc/integration/soc_zynq: fix HP0 connections <Florent Kermarrec>
    * | | a78ca2de - build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog) <Florent Kermarrec>
    |/ /
    * | a92e90b2 - soc/interconnect: add avalon with converters to/from native streams <Florent Kermarrec>
    * |   d860eeea - Merge pull request #162 from antmicro/full-conf-vexriscv <enjoy-digital>
    |\ \
    | * | 40de01bc - vexriscv: Add full and full_debug CPU variant <Joanna Brozek>
    * | |   ce81a39c - Merge pull request #163 from gsomlo/gls-verilated-cmdargs <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | e1683078 - build/sim/core: Initialize Verilator commandArgs <Gabriel L. Somlo>
    |/ /
    * | 017147c6 - build/altera: switch to sdc constraints, add add_false_path_constraints method <Florent Kermarrec>
    * | 1275e2f1 - build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints <Florent Kermarrec>
    * | c252972b - soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale <Florent Kermarrec>
    * | f986974d - soc/cores/clock: improve presentation <Florent Kermarrec>
    * | 538ca59a - build/xilinx/vivado: round period constraints to lowest picosecond <Florent Kermarrec>
    * |   66a74b15 - Merge pull request #161 from enjoy-digital/litex_server_arguments <enjoy-digital>
    |\ \
    | * | a2bc4bb7 - litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination <Florent Kermarrec>
    | * | be99083e - litex_server: add message and exit when mandarory arguments are missing. <Florent Kermarrec>
    | * | db11aec9 - litex_server: allow setting bind port, remove auto-incrementing on bind_port <Florent Kermarrec>
    | * | 76bc5785 - litex_server: refactor parameters and to allow setting bind address <Florent Kermarrec>
    |/ /
    * | 13a76ec7 - software/libnet/microudp: simplify txbuffer managment <Florent Kermarrec>
    * | 3441eb05 - software/libnet/microudp: cleanup eth_init <Florent Kermarrec>
    * | 92a79c6d - software/libnet/microudp: simplify rxbuffer managment <Florent Kermarrec>
    * | fdeff7f6 - software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE <Florent Kermarrec>
    * | 1569e2e0 - software/libnet: remove use of ethmac_mem.h <Florent Kermarrec>
    * | c7ac9676 - bios/sdram: add __attribute__((unused)) on cdelay <Florent Kermarrec>
    * | 7e53bff3 - litex_setup: add litesata <Florent Kermarrec>
    * | 792245f1 - boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter) <Florent Kermarrec>
    * | f8dcdb70 - software/libnet: add #ifdef on eth_init <Florent Kermarrec>
    * |   e475cfbb - Merge pull request #158 from vbuitvydas/altera-contrib <enjoy-digital>
    |\ \
    | * | 04939990 - litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name <vytautasb>
    | * | 8558065f - litex/build/altera/common: added reset synchronizer <vytautasb>
    |/ /
    * | 866fa344 - integration/soc_zynq: fix missing SoCCore.do_finalize <Florent Kermarrec>
    * | 794c3c58 - integration/soc_zynq: add add_hp0 method <Florent Kermarrec>
    * | 38d404c3 - integration/soc_zynq: use add methods to add optional peripherals <Florent Kermarrec>
    * | 7375856b - integration/soc_zynq: connect axi signals that were missing <Florent Kermarrec>
    * | b15fd9d8 - interconnect/axi: add missing axi signals <Florent Kermarrec>
    * |   f95748d1 - Merge pull request #157 from CBJamo/master <enjoy-digital>
    |\ \
    | * | 1f0b3f81 - Add ifdef check for MAIN_RAM_SIZE <Caleb Jamison>
    |/ /
    * | f452d3e9 - README: bump copyright year <Florent Kermarrec>
    * | dd214d2d - bios/main: align SoC info, show CPU speed on CPU line, show L2 <Florent Kermarrec>
    * | 6599f7bb - bios/main: move sdrinit <Florent Kermarrec>
    * | b92b89ab - bios/main: print boot sequence only if sdr_ok <Florent Kermarrec>
    * | f4369c8f - bios/main: remove csr functions (not used and only supported by lm32), improve help presentation <Florent Kermarrec>
    * | 66dffb70 - software/bios: improve readibility, add soc informations <Florent Kermarrec>
    * |   e8559990 - Merge pull request #156 from gsomlo/gls-axi-width <enjoy-digital>
    |\ \
    | * | 449632e4 - soc/interconnect/axi: data/address length cleanup <Gabriel L. Somlo>
    |/ /
    * | 552b0243 - soc/interconnect/axi: remove dead code (thanks gsomlo) <Florent Kermarrec>
    * |   b682dacd - Merge pull request #154 from daveshah1/yosys_xilinx_edif <enjoy-digital>
    |\ \
    | * | 57e1ccd5 - build/xilinx: Update Yosys write_edif parameters <David Shah>
    * | | fd7ed6c1 - utils/litex_sim: fix main_ram_size <Florent Kermarrec>
    * | | 3f386dad - soc_core/get_mem_data: add json support <Florent Kermarrec>
    * | | 7bc13ba8 - build/microsemi/libero_soc: add linux build script support <Florent Kermarrec>
    * | | 7b88980d - vexriscv: allow user to use an external variant <Florent Kermarrec>
    * | | b04a756a - vexriscv/core: fix min variant <Florent Kermarrec>
    * | | a549f094 - utils/litex_sim: handle cpu_endianness for rom-init/ram-init <Florent Kermarrec>
    * | | 411bca79 - utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified <Florent Kermarrec>
    * | |   7ec3ed4d - Merge pull request #153 from railnova/fix_utils <enjoy-digital>
    |\ \ \
    | * | | aed2e9b4 - [fix] utils was not installed from pip <chmousset>
    | |/ /
    * | |   3543b567 - Merge pull request #152 from gsomlo/gls-trellis-svf <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | b014c719 - build/lattice/trellis: also generate bitstream in svf format <Gabriel L. Somlo>
    |/ /
    * | 317dba83 - software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation <Florent Kermarrec>
    * | 7de1fe51 - targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC <Florent Kermarrec>
    * | ca63db40 - bios/sdram: use burstdet detection for ECP5DDRPHY init <Florent Kermarrec>
    |/
    *   2ebfab5e - Merge pull request #150 from daveshah1/trellis_bus_fixes <enjoy-digital>
    |\
    | * ebe8f600 - lattice/common: Fix tristate buses with Trellis <David Shah>
    |/
    * 935f3a53 - boards/ulx3s: add device selection parameter <Florent Kermarrec>
    * e6f97e08 - targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25 <Florent Kermarrec>
    * 5ef28bdf - build/lattice/trellis: add package support <Florent Kermarrec>
    * 1b34c07d - build/lattice/trellis: basecfg now integrated in nextpnr <Florent Kermarrec>
    * 7e995eb4 - boards/targets/ulx3s: allow building with diamond or trellis <Florent Kermarrec>
    * 4bf789ea - soc/software/bios/boot: add vexriscv workaround <Florent Kermarrec>
    * 1fd81c28 - soc/integration: add initial SoCZynq SoC <Florent Kermarrec>
    * 3c527dcb - soc/interconnect: add initial axi code with bus definition and AXI2Wishbone <Florent Kermarrec>
    * ed257879 - test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) <Florent Kermarrec>
    * 4aa07f2a - soc/interconnect: rename axi to axi_lite <Florent Kermarrec>
    * 6a4c133c - test: add basic test_csr <Florent Kermarrec>
    *   c9f9e237 - Merge pull request #149 from daveshah1/versa_trellis <enjoy-digital>
    |\
    | * ff7e0fab - versa_ecp5: Add option to build with Trellis <David Shah>
    | * 024b41c5 - trellis: Add LPF frequency constraints and remove -nomux <David Shah>
    * | e38dfd99 - soc/software/sdram: fix compilation on ultrascale <Florent Kermarrec>
    |/
    * 5f29a12e - targets/versa_ecp5: integrate DDR3 <Florent Kermarrec>
    * 3dd529e4 - soc/software/bios/sdram: add ECP5 support <Florent Kermarrec>
    * 2fd6d0e7 - soc/software/bios/sdram: improve write_level robustness <Florent Kermarrec>
    * 36772b75 - soc/software/bios/sdram: improve sdrlevel readibility <Florent Kermarrec>
    * 6a980781 - soc/software/bios/sdram: add helpers for rst/inc of delays <Florent Kermarrec>
    *   dad7b292 - Merge pull request #148 from daveshah1/versa_remove_n <enjoy-digital>
    |\
    | * 321dd8fc - versa_ecp5: Remove negative diff IO pins <David Shah>
    |/
    * c03b1ad1 - platforms/versa_ecp5: add ddram pins <Florent Kermarrec>
    * ff155a47 - soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write <Florent Kermarrec>
    * d3ecdd99 - soc/cores/clock: add actual clk_freqs to config <Florent Kermarrec>

 * migen changed from 0.6.dev-241-gafe4405 to 0.6.dev-283-g562c046
    * 562c046 - Correct URL of logo Signed-off-by: Chipmuenk <mail@chipmuenk.de> <Chipmuenk>
    * db7ce84 - updated packaging infos <Chipmuenk>
    * a9e5029 - platforms: add de10lite support <msloniewski>
    * a69e1fd - altera/quartus: fix generated build script <msloniewski>
    * 1b804d7 - platforms: add max1000 support <msloniewski>
    * bc90344 - metlino: v1.0rc5 <Sebastien Bourdeauducq>
    * 9031bfe - metlino: add VHDCI EEM carrier connector <Sebastien Bourdeauducq>
    * 83b209e - metlino: add LEDs, I2C, Si5324, transceivers <Sebastien Bourdeauducq>
    * 4289590 - metlino: set bitstream properties <Sebastien Bourdeauducq>
    * aea0841 - metlino: add gth_clk200 and port0 <Sebastien Bourdeauducq>
    * 7299f4e - metlino: add spiflash <Sebastien Bourdeauducq>
    * 6815691 - metlino: use same SDRAM constraints as Sayma <Sebastien Bourdeauducq>
    * 42fe506 - metlino: update pins to 1.0rc4 <Sebastien Bourdeauducq>
    * 54d666d - Lattice iCE40: add comment on the polarity of differential I/O pairs <airwoodix>
    * 090ece7 - Lattice iCE40: pass positive pin to SB_IO in DifferentialInput <airwoodix>
    * ee3508b - Revert e43cd74 <airwoodix>
    * e43cd74 - Lattice iCE40: fix DifferentialInput polarity <airwoodix>
    * e6d02be - humpback: fix serial pinouts (crossover cables) <airwoodix>
    * c8cae39 - Lattice iCE40: implement DifferentialInput <Etienne Wodey>
    * a6f9cbd - Add Sinara Humpback platform (#177) <Étienne Wodey>
    * 4e66a71 - Fix `-vlgincdir` for xst. <Tim 'mithro' Ansell>
    * edcadbc - sayma_rtm2: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq>
    * 49b9d8a - sayma_amc2: add rtm_amc_link <Sebastien Bourdeauducq>
    * 0080bed - sayma_rtm2: add AFE test pins <Sebastien Bourdeauducq>
    * 032340d - sayma_rtm2: add rtm_amc_link <Sebastien Bourdeauducq>
    * 8bf0ab8 - sayma_rtm2: fix clk50 IOStandard <Sebastien Bourdeauducq>
    * 5dc0b23 - sayma_rtm: select correct speed grade and IDCODE for v2 <Sebastien Bourdeauducq>
    * 98a075c - sayma_rtm: update for v2.0rc4 <Sebastien Bourdeauducq>
    * cd71a2a - fix permissions <Sebastien Bourdeauducq>
    * 5a843a1 - sayma_amc: update gth_clk200, add DDMTD signals <Sebastien Bourdeauducq>
    * 2154882 - sayma_amc: OVERTEMPPOWERDOWN is called OVERTEMPSHUTDOWN on Ultrascale <Sebastien Bourdeauducq>
    * 3773947 - sayma_amc: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq>
    * 383512b - sayma_amc2: update to v2.0rc4 <Sebastien Bourdeauducq>
    * 936732f - add sayma_rtm2 <Sebastien Bourdeauducq>
    * d482b93 - sayma_amc2: add ddrXX_clk <Sebastien Bourdeauducq>
    * 25646d4 - sayma_amc2: enable OVERTEMPPOWERDOWN <Sebastien Bourdeauducq>
    * 9fd7a48 - remove Roach <Sebastien Bourdeauducq>
    * 9d90900 - sayma_amc: use LVDS for serwb <Sebastien Bourdeauducq>
    * 3da7113 - sayma_amc: fix aux_clk I/O standard <Sebastien Bourdeauducq>
    * 9a25f90 - sayma_amc: fix v2 platform name <Sebastien Bourdeauducq>
    * 7765238 - add Sayma AMC v2 platform <Sebastien Bourdeauducq>
    * ae42105 - migen: replace `collections` with `collections.abc` as necessary (#176) <Sean Cross>

Full submodule status
--
 15df4aebf06da579241c58949493b866139d0e2b edid-decode (remotes/origin/HEAD)
 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 flash_proxies (heads/master)
 67de3cee14b13beabc90804e3b62c66e028fd951 litedram (heads/master)
 2424e62bf9637c2623b627a56aca7a3f90349e92 liteeth (heads/master)
 de6cd01d3f158387337bf4f47fd5a351ec2c3267 litepcie (heads/master)
 6fe4cceaab77d6a117fa539f461b3ae9ca7e668e litesata (heads/master)
 2474ce9db23e4d06bff4bbeacf0051efa3042f37 litescope (heads/master)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
 98e145fba8c25394e9958bad67e2a457d145127e litevideo (heads/master)
 113f7f408e7c95150011c55ca473f45befb7f9bb litex (remotes/origin/HEAD)
 562c0466443f859d6cf0c87a0bb50db094d27cf4 migen (0.6.dev-283-g562c046)
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