Add support for more boards

.travis.yml

@@ -86,6 +86,24 @@ jobs:
   - stage: Targets - Base
     env: C=lm32 P=pipistrello  T="base"
 
+  - stage: Targets - Base
+    env: C=lm32 P=saturn       T="base"
+
+  - stage: Targets - Base
+    env: C=lm32 P=galatea      T="base"
+
+  - stage: Targets - Base
+    env: C=lm32 P=neso         T="base"
+
+  - stage: Targets - Base
+    env: C=lm32 P=waxwing      T="base"
+
+  - stage: Targets - Base
+    env: C=lm32 P=basys3       T="base"
+
+  - stage: Targets - Base
+    env: C=lm32 P=cmod_a7      T="base"
+
   # or1k base targets
   - stage: Targets - Base
     env: C=or1k P=arty         T="base net"

firmware/framebuffer.h

@@ -14,6 +14,7 @@
 #ifndef __FRAMEBUFFER_H
 #define __FRAMEBUFFER_H
 
+#include <assert.h>
 #include <stdint.h>
 #include "generated/mem.h"
 
@@ -62,7 +63,13 @@ typedef unsigned int fb_ptrdiff_t;
 // FIXME: typedef uint16_t framebuffer_t[FRAMEBUFFER_SIZE];
 
 inline unsigned int *fb_ptrdiff_to_main_ram(fb_ptrdiff_t p) {
+#ifdef MAIN_RAM_BASE
 	return (unsigned int *)(MAIN_RAM_BASE + p);
+#else
+/*       FIXME!  Should be unreachable if we have no main ram! */
+        assert(0);
+        return (unsigned int *)(0);
+#endif
 }
 
 #endif /* __FRAMEBUFFER_H */

firmware/pattern.c

@@ -132,6 +132,7 @@ static int inc_color(int color) {
 }
 
 static void pattern_draw_text_color(int x, int y, char *ptr, long background_color, long text_color) {
+#ifdef MAIN_RAM_BASE
 	int i, j, k;
 	int adr;
 	volatile unsigned int *framebuffer = (unsigned int *)(MAIN_RAM_BASE + pattern_framebuffer_base());
@@ -149,6 +150,8 @@ static void pattern_draw_text_color(int x, int y, char *ptr, long background_col
 			}
 		}
 	}
+/* FIXME: Framebuffer Should not even be compiled if no MAIN RAM */
+#endif
 }
 
 static void pattern_draw_text(int x, int y, char *ptr) {
@@ -164,6 +167,7 @@ void pattern_next(void) {
 
 void pattern_fill_framebuffer(int h_active, int w_active)
 {
+#ifdef MAIN_RAM_BASE
 	int i, j;
 	int color;
 	flush_l2_cache();
@@ -242,10 +246,13 @@ void pattern_fill_framebuffer(int h_active, int w_active)
 #endif
 
 	flush_l2_cache();
+/* FIXME: Framebuffer Should not even be compiled if no MAIN RAM */
+#endif
 }
 
 void pattern_service(void)
 {
+#ifdef MAIN_RAM_BASE
 	static int last_event;
 	static char buffer[16];
 
@@ -254,4 +261,6 @@ void pattern_service(void)
 		pattern_draw_text(1, 1, buffer);
 	}
 	flush_l2_cache();
+/* FIXME: Framebuffer Should not even be compiled if no MAIN RAM */
+#endif
 }

platforms/basys3.py

@@ -0,0 +1,113 @@
+# This file is Copyright (c) 2015 Yann Sionneau <yann@sionneau.net>
+# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+from litex.build.generic_platform import *
+from litex.build.openocd import OpenOCD
+from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
+
+_io = [
+    ("user_led", 0, Pins("U16"), IOStandard("LVCMOS33")),
+    ("user_led", 1, Pins("E19"), IOStandard("LVCMOS33")),
+    ("user_led", 2, Pins("U19"), IOStandard("LVCMOS33")),
+    ("user_led", 3, Pins("V19"), IOStandard("LVCMOS33")),
+    ("user_led", 4, Pins("W18"), IOStandard("LVCMOS33")),
+    ("user_led", 5, Pins("U15"), IOStandard("LVCMOS33")),
+    ("user_led", 6, Pins("U14"), IOStandard("LVCMOS33")),
+    ("user_led", 7, Pins("V14"), IOStandard("LVCMOS33")),
+    ("user_led", 8, Pins("V13"), IOStandard("LVCMOS33")),
+    ("user_led", 9, Pins("V3"), IOStandard("LVCMOS33")),
+    ("user_led", 10, Pins("W3"), IOStandard("LVCMOS33")),
+    ("user_led", 11, Pins("U3"), IOStandard("LVCMOS33")),
+    ("user_led", 12, Pins("P3"), IOStandard("LVCMOS33")),
+    ("user_led", 13, Pins("N3"), IOStandard("LVCMOS33")),
+    ("user_led", 14, Pins("P1"), IOStandard("LVCMOS33")),
+    ("user_led", 15, Pins("L1"), IOStandard("LVCMOS33")),
+
+    ("user_sw", 0, Pins("V17"), IOStandard("LVCMOS33")),
+    ("user_sw", 1, Pins("V16"), IOStandard("LVCMOS33")),
+    ("user_sw", 2, Pins("W16"), IOStandard("LVCMOS33")),
+    ("user_sw", 3, Pins("W17"), IOStandard("LVCMOS33")),
+    ("user_sw", 4, Pins("W15"), IOStandard("LVCMOS33")),
+    ("user_sw", 5, Pins("V15"), IOStandard("LVCMOS33")),
+    ("user_sw", 6, Pins("W14"), IOStandard("LVCMOS33")),
+    ("user_sw", 7, Pins("W13"), IOStandard("LVCMOS33")),
+    ("user_sw", 8, Pins("V2"), IOStandard("LVCMOS33")),
+    ("user_sw", 9, Pins("T3"), IOStandard("LVCMOS33")),
+    ("user_sw", 10, Pins("T2"), IOStandard("LVCMOS33")),
+    ("user_sw", 11, Pins("R3"), IOStandard("LVCMOS33")),
+    ("user_sw", 12, Pins("W2"), IOStandard("LVCMOS33")),
+    ("user_sw", 13, Pins("U1"), IOStandard("LVCMOS33")),
+    ("user_sw", 14, Pins("T1"), IOStandard("LVCMOS33")),
+    ("user_sw", 15, Pins("R2"), IOStandard("LVCMOS33")),
+
+    ("user_btn", 0, Pins("W19"), IOStandard("LVCMOS33")),
+    ("user_btn", 1, Pins("T17"), IOStandard("LVCMOS33")),
+    ("user_btn", 2, Pins("T18"), IOStandard("LVCMOS33")),
+    ("user_btn", 3, Pins("U17"), IOStandard("LVCMOS33")),
+    ("user_btn", 4, Pins("U18"), IOStandard("LVCMOS33")),
+
+    ("clk100", 0, Pins("W5"), IOStandard("LVCMOS33")),
+
+    ("serial", 0,
+        Subsignal("tx", Pins("A18")),
+        Subsignal("rx", Pins("B18")),
+        IOStandard("LVCMOS33")),
+
+    ("spiflash_4x", 0,  # clock needs to be accessed through STARTUPE2
+        Subsignal("cs_n", Pins("K19")),
+        Subsignal("dq", Pins("D18", "D19", "G18", "F18")),
+        IOStandard("LVCMOS33")
+    ),
+    ("spiflash_1x", 0,  # clock needs to be accessed through STARTUPE2
+        Subsignal("cs_n", Pins("K19")),
+        Subsignal("mosi", Pins("D18")),
+        Subsignal("miso", Pins("D19")),
+        Subsignal("wp", Pins("G18")),
+        Subsignal("hold", Pins("F18")),
+        IOStandard("LVCMOS33")
+    ),
+]
+
+
+class Platform(XilinxPlatform):
+    name = "basys3"
+    default_clk_name = "clk100"
+    default_clk_period = 10.0
+
+    # From https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+    # 17536096 bits == 2192012 == 0x21728c -- Therefore 0x220000
+    gateware_size = 0x220000
+
+    # Micron N25Q128A13ESF40 (ID 0x0018ba20)
+    # FIXME: Create a "spi flash module" object in the same way we have SDRAM
+    # module objects.
+    spiflash_model = "n25q128a13"
+    spiflash_read_dummy_bits = 10
+    spiflash_clock_div = 4
+    spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
+    spiflash_page_size = 256
+    spiflash_sector_size = 0x10000
+
+    def __init__(self, toolchain="vivado", programmer="openocd"):
+        XilinxPlatform.__init__(self, "xc7a35t-cpg236-1", _io,
+                                toolchain=toolchain)
+        self.toolchain.bitstream_commands = \
+            ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
+        self.toolchain.additional_commands = \
+            ["write_cfgmem -force -format bin -interface spix4 -size 16 "
+             "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+        self.programmer = programmer
+        self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
+
+    def create_programmer(self):
+        if self.programmer == "openocd":
+            proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
+            return OpenOCD(config="board/digilent_arty.cfg", flash_proxy_basename=proxy)
+        elif self.programmer == "xc3sprog":
+            return XC3SProg("nexys4")
+        elif self.programmer == "vivado":
+            return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
+        else:
+            raise ValueError("{} programmer is not supported"
+                             .format(self.programmer))

platforms/cmod_a7.py

@@ -0,0 +1,177 @@
+# This file is Copyright (c) 2017 Tim 'mithro' Ansell <mithro@mithro.com>
+# License: BSD
+
+from litex.build.generic_platform import *
+from litex.build.openocd import OpenOCD
+from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+
+_io = [
+
+    ## LEDs
+    #set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1]
+    #set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
+    ("user_led", 0, Pins("A17"), IOStandard("LVCMOS33")),
+    ("user_led", 1, Pins("C16"), IOStandard("LVCMOS33")),
+
+    #set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L14N_T2_SRCC_16 Sch=led0_b
+    #set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L13N_T2_MRCC_16 Sch=led0_g
+    #set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L14P_T2_SRCC_16 Sch=led0_r
+    ("rgb_leds", 0,
+        Subsignal("r", Pins("C17")),
+        Subsignal("g", Pins("B16")),
+        Subsignal("b", Pins("B17")),
+        IOStandard("LVCMOS33")
+    ),
+
+    ## Buttons
+    #set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
+    #set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1]
+    ("user_btn", 0, Pins("A18"), IOStandard("LVCMOS33")),
+    ("user_btn", 1, Pins("B18"), IOStandard("LVCMOS33")),
+
+    ## Clock signal 12 MHz
+    #set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
+    #create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];
+    ("clk12", 0, Pins("L17"), IOStandard("LVCMOS33")),
+
+    ## UART
+    #set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
+    #set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in  }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
+    ("serial", 0,
+        Subsignal("tx", Pins("J18")),
+        Subsignal("rx", Pins("J17")),
+        IOStandard("LVCMOS33")),
+
+    ## QSPI - N25Q032A13EF440F
+    #set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs    }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+    #set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+    #set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+    #set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+    #set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+    ("spiflash_4x", 0,  # clock needs to be accessed through STARTUPE2
+        Subsignal("cs_n", Pins("K19")),
+        Subsignal("dq", Pins("D18", "D19", "G18", "F18")),
+        IOStandard("LVCMOS33")
+    ),
+    ("spiflash_1x", 0,  # clock needs to be accessed through STARTUPE2
+        Subsignal("cs_n", Pins("K19")),
+        Subsignal("mosi", Pins("D18")), # DQ0
+        Subsignal("miso", Pins("D19")), # DQ1
+        Subsignal("wp",   Pins("G18")), # DQ2
+        Subsignal("hold", Pins("F18")), # DQ3
+        IOStandard("LVCMOS33")
+    ),
+
+    ## SRAM
+    ## 512KB SRAM with an 8-bit bus and 8ns access times
+    #set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[0]  }]; #IO_L11P_T1_SRCC_14 Sch=sram- a[0]
+    #set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[1]  }]; #IO_L11N_T1_SRCC_14 Sch=sram- a[1]
+    #set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[2]  }]; #IO_L12N_T1_MRCC_14 Sch=sram- a[2]
+    #set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[3]  }]; #IO_L13P_T2_MRCC_14 Sch=sram- a[3]
+    #set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[4]  }]; #IO_L13N_T2_MRCC_14 Sch=sram- a[4]
+    #set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[5]  }]; #IO_L14P_T2_SRCC_14 Sch=sram- a[5]
+    #set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[6]  }]; #IO_L14N_T2_SRCC_14 Sch=sram- a[6]
+    #set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[7]  }]; #IO_L16N_T2_A15_D31_14 Sch=sram- a[7]
+    #set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[8]  }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram- a[8]
+    #set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[9]  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram- a[9]
+    #set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[10] }]; #IO_L16P_T2_CSI_B_14 Sch=sram- a[10]
+    #set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[11] }]; #IO_L17P_T2_A14_D30_14 Sch=sram- a[11]
+    #set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[12] }]; #IO_L17N_T2_A13_D29_14 Sch=sram- a[12]
+    #set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[13] }]; #IO_L18P_T2_A12_D28_14 Sch=sram- a[13]
+    #set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[14] }]; #IO_L18N_T2_A11_D27_14 Sch=sram- a[14]
+    #set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[15] }]; #IO_L19P_T3_A10_D26_14 Sch=sram- a[15]
+    #set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[16] }]; #IO_L20P_T3_A08_D24_14 Sch=sram- a[16]
+    #set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[17] }]; #IO_L20N_T3_A07_D23_14 Sch=sram- a[17]
+    #set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[18] }]; #IO_L21P_T3_DQS_14 Sch=sram- a[18]
+    #set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[0]   }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram-dq[0]
+    #set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[1]   }]; #IO_L22P_T3_A05_D21_14 Sch=sram-dq[1]
+    #set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[2]   }]; #IO_L22N_T3_A04_D20_14 Sch=sram-dq[2]
+    #set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[3]   }]; #IO_L23P_T3_A03_D19_14 Sch=sram-dq[3]
+    #set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { MemDB[4]   }]; #IO_L23N_T3_A02_D18_14 Sch=sram-dq[4]
+    #set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[5]   }]; #IO_L24P_T3_A01_D17_14 Sch=sram-dq[5]
+    #set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[6]   }]; #IO_L24N_T3_A00_D16_14 Sch=sram-dq[6]
+    #set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[7]   }]; #IO_25_14 Sch=sram-dq[7]
+    #set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { RamOEn     }]; #IO_L10P_T1_D14_14 Sch=sram-oe
+    #set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { RamWEn     }]; #IO_L10N_T1_D15_14 Sch=sram-we
+    #set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS33 } [get_ports { RamCEn     }]; #IO_L9N_T1_DQS_D13_14 Sch=sram-ce
+    ("sram", 0,
+        Subsignal(
+            "a",
+            Pins("M18 M19 K17 N17 P17 P18 R18 W19",
+                 "U19 V19 W18 T17 T18 U17 U18 V16",
+                 "W16 W17 V15"),
+            IOStandard("LVCMOS33")),
+        Subsignal(
+            "dq",
+            Pins("W15 W13 W14 U15 U16 V13 V14 U14"),
+            IOStandard("LVCMOS33")),
+        Subsignal("oe_n", Pins("R19"), IOStandard("LVCMOS33")),
+        Subsignal("we_n", Pins("R19"), IOStandard("LVCMOS33")),
+        Subsignal("ce_n", Pins("N19"), IOStandard("LVCMOS33")),
+        Misc("SLEW=FAST"),
+    ),
+
+    ## Analog XADC Pins
+    ## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
+    #set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
+    #set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
+    #set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
+    #set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]
+
+    ## Crypto 1 Wire Interface - ATSHA204A-MAHCZ-T
+    #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_0_14 Sch=crypto_sda
+
+    ## Pmod Header JA
+    #set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L5N_T0_D07_14 Sch=ja[1]
+    #set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja[2]
+    #set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L9P_T1_DQS_14 Sch=ja[3]
+    #set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L8P_T1_D11_14 Sch=ja[4]
+    #set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7]
+    #set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L4P_T0_D04_14 Sch=ja[8]
+    #set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L6N_T0_D08_VREF_14 Sch=ja[9]
+    #set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja[10]
+]
+
+
+class Platform(XilinxPlatform):
+    name = "cmod_a7"
+    default_clk_name = "clk12"
+    default_clk_period = 1e9/12e6
+
+    # From https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+    # 17536096 bits == 2192012 == 0x21728c -- Therefore 0x220000
+    gateware_size = 0x220000
+
+    # Micron N25Q032A13EF440F (ID 0x0016ba20)
+    # 3V, Multiple I/O, 4KB Sector Erase
+    # 108 MHz (MAX) clock frequency
+    # FIXME: Create a "spi flash module" object in the same way we have SDRAM
+    # module objects.
+    spiflash_model = "n25q32"
+    spiflash_read_dummy_bits = 10
+    spiflash_clock_div = 4
+    spiflash_total_size = int((32/8)*1024*1024) # 32MMbit
+    spiflash_page_size = 256
+    spiflash_sector_size = 0x10000
+
+    def __init__(self, toolchain="vivado", programmer="openocd"):
+        XilinxPlatform.__init__(self, "xc7a35t-cpg236-1", _io,
+                                toolchain=toolchain)
+        self.toolchain.bitstream_commands = \
+            ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
+        self.toolchain.additional_commands = \
+            ["write_cfgmem -force -format bin -interface spix4 -size 16 "
+             "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+        self.programmer = programmer
+        self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
+
+    def create_programmer(self):
+        if self.programmer == "openocd":
+            proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
+            return OpenOCD(config="board/digilent_cmod_a7.cfg", flash_proxy_basename=proxy)
+        elif self.programmer == "vivado":
+            # n25q32-3.3v-spi-x1_x2_x4
+            return VivadoProgrammer(flash_part="n25q32-3.3v-spi-x1_x2_x4")
+        else:
+            raise ValueError(
+                "{} programmer is not supported".format(self.programmer))