(Verilog+MIPS+FPGA MINISYS) (121/100): Single Cycle CPU: Our project of CS202 2023 Spring: Computer Organization, SUSTech. Taught by Prof. Jin ZHANG.
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Updated
Mar 22, 2024 - SystemVerilog
(Verilog+MIPS+FPGA MINISYS) (121/100): Single Cycle CPU: Our project of CS202 2023 Spring: Computer Organization, SUSTech. Taught by Prof. Jin ZHANG.
(1120/1100) Labs of CS208 2023 Spring: Algorithm Design and Analysis (ADA), SUSTech. Taught by Prof. Yuhui SHI.
(Spark+PSQL/OpenGauss) (96/100,102/100) Forum Database: Our projects of CS307 2023 Spring: Database Principle, SUSTech. Taught by Prof. Yuxin MA.
(Mininet+Ryu Controller) (103/100) SDN with DHCP and SP switching: Our Project of CS305 2023 Spring: Computer Network, SUSTech. Taught by Prof. Zhuozhao LI @ZhuozhaoLi.
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