Simple equalization circuit specified using VHDL
-
Updated
Nov 10, 2021 - VHDL
Simple equalization circuit specified using VHDL
Final project of the course Reti Logiche (Digital Logic Design) at Politecnico di Milano
Add a description, image, and links to the equalization topic page so that developers can more easily learn about it.
To associate your repository with the equalization topic, visit your repo's landing page and select "manage topics."