This is Amirkabir University Logic Circuit Design final project 2022
-
Updated
Aug 5, 2022 - C
This is Amirkabir University Logic Circuit Design final project 2022
Different adders code in VHDL and Comparison
An adder is a digital circuit that performs addition of numbers. Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM.
Testers for some non elementary integrated circuits: Adder 74283, D Flip-Flop 74174 & Counter 74193 written to be run from PSoC 4
Add a description, image, and links to the full-adder topic page so that developers can more easily learn about it.
To associate your repository with the full-adder topic, visit your repo's landing page and select "manage topics."