Simulates a memory-subsystem encompassing a bi-level TLB and a bi-level cache system along with a main memory following segmentation with paging with all different replacement policies
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Updated
Apr 5, 2020 - C
Simulates a memory-subsystem encompassing a bi-level TLB and a bi-level cache system along with a main memory following segmentation with paging with all different replacement policies
One-level page table system with FIFO and LRU and Two-level page table system with LRU and Inverted page table with a hashing system
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