simulation of a multi-core (with an arbitrary number of cores) cache, including set associativity, with simple MSI cache coherency.
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Updated
Jun 17, 2018 - C
simulation of a multi-core (with an arbitrary number of cores) cache, including set associativity, with simple MSI cache coherency.
Heo is a cycle-accurate multicore architectural simulator written in Go.
Simulator for Coherence protocol, parallel programming acceleration with OpenMP, MPI, Hybrid
ConvLIB is a library of convolution kernels for multicore processors with ARM (NEON) or RISC-V architecture
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