VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
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Updated
Jan 4, 2022 - Verilog
VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
PLL x8 clock multiplier IP integrated onto the Efabless Caravel SoC
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