SerDes RTL design, verification using UVM and Physical design.
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Updated
May 26, 2024 - Verilog
SerDes RTL design, verification using UVM and Physical design.
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
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