An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
fpga
hls
vlsi
hardware-acceleration
high-level-synthesis
stencils
hardware-description-language
vivado-hls
vlsi-design
stencil-computations
vitis-hls
-
Updated
Sep 13, 2022 - C++