A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

DaCH: dataflow cache for high-level synthesis.

Advanced multi-band GNSS SDR front-end implementation in an RFSoC integrated circuit. GPL-3.0 license

FPGA Acceleration for the LoFreq variant caller

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Mixing HLS and Backend Versions in Vitis

Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)

Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs

Xilinx Tools Tutorials

Vitis HLS cmake integration

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

Vitis (Vivado) HLS Examples

An accelerated implementation of the kNN algorithm on the Kria KV260 FPGA

Xilinx Vitis HLS 2022.2 bug sample

tinyVTA - A General Purpose FPGA-based DNN Accelerator

Hardware accelerator for Image processing in FPGA

This is an indie Electronic Fuel Injection System project that's been inherited from our sensẽi, Mr NQA. This project is a big bravo to the rest of my teammate, we've all been trying to do our best and we do.