Deep learning toolkit-enabled VLSI placement
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Updated
Jun 26, 2024 - C++
Deep learning toolkit-enabled VLSI placement
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
VLSI EDA Global Router
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Steiner Shallow-Light Tree for VLSI Routing
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
Coursework of NTHU CS613500 VLSI Physical Design Automation
A SAT-Based cell router.
A customized placer based on the RePlAce global placement tool.
Design rule checker for VLSI layouts
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