A High-performance Timing Analysis Tool for VLSI Systems

Standard Cell Library based Memory Compiler using FF/Latch cells

A Standalone Structural Verilog Parser

DATC RDF

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisa…

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

5 Day TCL begginer to advanced training workshop by VSD

This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

IEEE DATC Robust Design Flow 2021.

RTL to GDSII Physical Design using OpenLane and Opensource Softwares

Complete design of USART interface with baud rate selection

In electronics, a multiplexer (or mux; spelled sometimes as multiplexer, also known as a data selector, is a device that selects between several analog or digital input signals and forwards the selected input to a single output line.