tqma6: update spl to Rev. 0300D

Signed-off-by: Max Merchel <Max.Merchel@tq-group.com>
tq-systems · Feb 1, 2018 · 15eb6ab · 15eb6ab
1 parent c12ad12
commit 15eb6ab
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Showing 8 changed files with 82 additions and 77 deletions.
diff --git a/board/tqc/tqma6/tqma6dl.c b/board/tqc/tqma6/tqma6dl.c
@@ -30,7 +30,7 @@ static inline void init_write_reg(uint32_t address, uint32_t value)
 static void tqma6dl_init_ddr_controller(void)
 {
 	debug("spl: tqma6dl ddr iom ....\n");
-	/* TQMa6DL DDR config Rev. 0100E */
+	/* TQMa6DL DDR config Rev. 0300D */
 	/* IOMUX configuration */
 	init_write_reg(MX6_IOM_GRP_DDR_TYPE, 0x000C0000);
 	init_write_reg(MX6_IOM_GRP_DDRPKE, 0x00000000);
@@ -39,7 +39,7 @@ static void tqma6dl_init_ddr_controller(void)
 	init_write_reg(MX6_IOM_DRAM_CAS, 0x00008030);
 	init_write_reg(MX6_IOM_DRAM_RAS, 0x00008030);
 	init_write_reg(MX6_IOM_GRP_ADDDS, 0x00000030);
-	init_write_reg(MX6_IOM_DRAM_RESET, 0x000C3030);
+	init_write_reg(MX6_IOM_DRAM_RESET, 0x00000030);
 	init_write_reg(MX6_IOM_DRAM_SDCKE0, 0x00003000);
 	init_write_reg(MX6_IOM_DRAM_SDCKE1, 0x00000000);
 	init_write_reg(MX6_IOM_DRAM_SDBA2, 0x00000000);
@@ -112,7 +112,7 @@ static void tqma6dl_init_ddr_controller(void)
 	init_write_reg(MX6_MMDC_P0_MDCFG0, 0x3F435333);
 	init_write_reg(MX6_MMDC_P0_MDCFG1, 0xB68E8B63);
 	init_write_reg(MX6_MMDC_P0_MDCFG2, 0x01FF00DB);
-	init_write_reg(MX6_MMDC_P0_MDMISC, 0x00001740);
+	init_write_reg(MX6_MMDC_P0_MDMISC, 0x00011740);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000);
 
 	debug("spl: tqma6dl MX6_MMDC_P0_MDSCR %x ....\n", __raw_readl(MX6_MMDC_P0_MDSCR));
@@ -121,15 +121,15 @@ static void tqma6dl_init_ddr_controller(void)
 	init_write_reg(MX6_MMDC_P0_MDRWD, 0x000026D2);
 	init_write_reg(MX6_MMDC_P0_MDOR, 0x00431023);
 	init_write_reg(MX6_MMDC_P0_MDASP, 0x00000027);
-	
+
 	debug("spl: tqma6dl ddr mdctl - leave reset\n");
 	init_write_reg(MX6_MMDC_P0_MDCTL, 0x831A0000);
 
 /* TODO: wait to CKE ???? */
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00408032);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008033);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00048031);
-	init_write_reg(MX6_MMDC_P0_MDSCR, 0x05208030);
+	init_write_reg(MX6_MMDC_P0_MDSCR, 0x15208030);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x04008040);
 	init_write_reg(MX6_MMDC_P0_MDREF, 0x00007800);
 	init_write_reg(MX6_MMDC_P0_MPODTCTRL, 0x00022222);

diff --git a/board/tqc/tqma6/tqma6dl.cfg b/board/tqc/tqma6/tqma6dl.cfg
@@ -29,7 +29,7 @@ BOOT_FROM      spi
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
 
-/* TQMa6DL DDR config Rev. 0100E */
+/* TQMa6DL DDR config Rev. 0300D */
 /* IOMUX configuration */
 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
@@ -38,7 +38,7 @@ DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
 DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
 DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
@@ -104,16 +104,17 @@ DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
 DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
 DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
 DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
 DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
 DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
 DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
 DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x15208030
 DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
 DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
 DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222

diff --git a/board/tqc/tqma6/tqma6q.c b/board/tqc/tqma6/tqma6q.c
@@ -31,7 +31,7 @@ static inline void init_write_reg(uint32_t address, uint32_t value)
 static void tqma6q_init_ddr_controller(void)
 {
 	debug("spl: tqma6q ddr iom ....\n");
-	/* TQMa6Q/D DDR config Rev. 0100B */
+	/* TQMa6Q/D DDR config Rev. 0300D */
 	/* IOMUX configuration */
 	init_write_reg(MX6_IOM_GRP_DDR_TYPE, 0x000C0000);
 	init_write_reg(MX6_IOM_GRP_DDRPKE, 0x00000000);
@@ -40,7 +40,7 @@ static void tqma6q_init_ddr_controller(void)
 	init_write_reg(MX6_IOM_DRAM_CAS, 0x00008030);
 	init_write_reg(MX6_IOM_DRAM_RAS, 0x00008030);
 	init_write_reg(MX6_IOM_GRP_ADDDS, 0x00000030);
-	init_write_reg(MX6_IOM_DRAM_RESET, 0x000C3030);
+	init_write_reg(MX6_IOM_DRAM_RESET, 0x00000030);
 	init_write_reg(MX6_IOM_DRAM_SDCKE0, 0x00003000);
 	init_write_reg(MX6_IOM_DRAM_SDCKE1, 0x00000000);
 	init_write_reg(MX6_IOM_DRAM_SDBA2, 0x00000000);
@@ -67,7 +67,7 @@ static void tqma6q_init_ddr_controller(void)
 	init_write_reg(MX6_IOM_GRP_B5DS, 0x00000030);
 	init_write_reg(MX6_IOM_GRP_B6DS, 0x00000030);
 	init_write_reg(MX6_IOM_GRP_B7DS, 0x00000030);
-	
+
 	init_write_reg(MX6_IOM_DRAM_DQM0, 0x00000030);
 	init_write_reg(MX6_IOM_DRAM_DQM1, 0x00000030);
 	init_write_reg(MX6_IOM_DRAM_DQM2, 0x00000030);
@@ -81,21 +81,21 @@ static void tqma6q_init_ddr_controller(void)
 	/* memory interface calibration values */
 	init_write_reg(MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003);
 	init_write_reg(MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003);
-	
-	init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013);
-	init_write_reg(MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B);
-	init_write_reg(MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016);
-	init_write_reg(MX6_MMDC_P1_MPWLDECTRL1, 0x0012001c);
-	
-	init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x43400350);
-	init_write_reg(MX6_MMDC_P0_MPDGCTRL1, 0x023E032C);
-	init_write_reg(MX6_MMDC_P1_MPDGCTRL0, 0x43400348);
-	init_write_reg(MX6_MMDC_P1_MPDGCTRL1, 0x03300304);
-	
-	init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x3C323436);
-	init_write_reg(MX6_MMDC_P1_MPRDDLCTL, 0x38383242);
-	init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440);
-	init_write_reg(MX6_MMDC_P1_MPWRDLCTL, 0x4236483E);
+
+	init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00180016);
+	init_write_reg(MX6_MMDC_P0_MPWLDECTRL1, 0x001F0018);
+	init_write_reg(MX6_MMDC_P1_MPWLDECTRL0, 0x00130023);
+	init_write_reg(MX6_MMDC_P1_MPWLDECTRL1, 0x00040018);
+
+	init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x43500364);
+	init_write_reg(MX6_MMDC_P0_MPDGCTRL1, 0x034C0344);
+	init_write_reg(MX6_MMDC_P1_MPDGCTRL0, 0x43580364);
+	init_write_reg(MX6_MMDC_P1_MPDGCTRL1, 0x033C031C);
+
+	init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x3C323438);
+	init_write_reg(MX6_MMDC_P1_MPRDDLCTL, 0x383A3040);
+	init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x3A3E4440);
+	init_write_reg(MX6_MMDC_P1_MPWRDLCTL, 0x4834483A);
 	init_write_reg(MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333);
 	init_write_reg(MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333);
 	init_write_reg(MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333);
@@ -114,25 +114,25 @@ static void tqma6q_init_ddr_controller(void)
 	init_write_reg(MX6_MMDC_P0_MDCFG0, 0x545A79B4);
 	init_write_reg(MX6_MMDC_P0_MDCFG1, 0xDB538F64);
 	init_write_reg(MX6_MMDC_P0_MDCFG2, 0x01FF00DB);
-	init_write_reg(MX6_MMDC_P0_MDMISC, 0x00001740);
+	init_write_reg(MX6_MMDC_P0_MDMISC, 0x00011740);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000);
 
 	debug("spl: tqma6q MX6_MMDC_P0_MDSCR %x ....\n", __raw_readl(MX6_MMDC_P0_MDSCR));
 /* TODO: leave it in Power Up Default */
 	init_write_reg(MX6_MMDC_P0_MDRWD, 0x000026D2);
 	init_write_reg(MX6_MMDC_P0_MDOR, 0x005A1023);
 	init_write_reg(MX6_MMDC_P0_MDASP, 0x00000027);
-	
+
 	debug("spl: tqma6q ddr mdctl - leave reset\n");
 	init_write_reg(MX6_MMDC_P0_MDCTL, 0x831A0000);
 
 /* TODO: wait to CKE ???? */
-	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00088032);
+	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00488032);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008033);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00048031);
-	init_write_reg(MX6_MMDC_P0_MDSCR, 0x09308030);
+	init_write_reg(MX6_MMDC_P0_MDSCR, 0x19308030);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x04008040);
-	init_write_reg(MX6_MMDC_P0_MDREF, 0x00005800);
+	init_write_reg(MX6_MMDC_P0_MDREF, 0x00007800);
 	init_write_reg(MX6_MMDC_P0_MPODTCTRL, 0x00022222);
 	init_write_reg(MX6_MMDC_P1_MPODTCTRL, 0x00022222);
 	init_write_reg(MX6_MMDC_P0_MDPDC, 0x00025536);

diff --git a/board/tqc/tqma6/tqma6q.cfg b/board/tqc/tqma6/tqma6q.cfg
@@ -29,7 +29,7 @@ BOOT_FROM      spi
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
 
-/* TQMa6Q/D DDR config Rev. 0100B */
+/* TQMa6Q/D DDR config Rev. 0300D */
 /* IOMUX configuration */
 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
@@ -38,7 +38,7 @@ DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
 DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
 DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
@@ -75,18 +75,18 @@ DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
 /* memory interface calibration values */
 DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
 DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00180016
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F0018
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00130023
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00040018
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43500364
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0344
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43580364
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x033C031C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323438
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x383A3040
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3E4440
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4834483A
 DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
 DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
 DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
@@ -104,22 +104,24 @@ DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
 DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4
 DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
 DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
 DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
 DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
 DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
 DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00488032
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
 DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
 DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
 DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
 DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536
 DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
 
+
 #include "clocks.cfg"
diff --git a/board/tqc/tqma6/tqma6qp.c b/board/tqc/tqma6/tqma6qp.c
@@ -31,7 +31,7 @@ static inline void init_write_reg(uint32_t address, uint32_t value)
 static void tqma6qp_init_ddr_controller(void)
 {
 	debug("spl: tqma6qp ddr iom ....\n");
-	/* TQMa6QP DDR config Rev. 0300C */
+	/* TQMa6QP DDR config Rev. 0300D */
 	/* IOMUX configuration */
 	init_write_reg(MX6_IOM_GRP_DDR_TYPE, 0x000C0000);
 	init_write_reg(MX6_IOM_GRP_DDRPKE, 0x00000000);

diff --git a/board/tqc/tqma6/tqma6qp.cfg b/board/tqc/tqma6/tqma6qp.cfg
@@ -29,7 +29,7 @@ BOOT_FROM      spi
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
 
-/* TQMa6DQP DDR config Rev. 0300C */
+/* TQMa6DQP DDR config Rev. 0300D */
 /* IOMUX configuration */
 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000

diff --git a/board/tqc/tqma6/tqma6s.c b/board/tqc/tqma6/tqma6s.c
@@ -30,7 +30,7 @@ static inline void init_write_reg(uint32_t address, uint32_t value)
 static void tqma6s_init_ddr_controller(void)
 {
 	debug("spl: tqma6s ddr iom ....\n");
-	/* TQMa6S DDR config Rev. 0100B */
+	/* TQMa6S DDR config Rev. 0300D */
 	/* IOMUX configuration */
 	init_write_reg(MX6_IOM_GRP_DDR_TYPE, 0x000C0000);
 	init_write_reg(MX6_IOM_GRP_DDRPKE, 0x00000000);
@@ -39,7 +39,7 @@ static void tqma6s_init_ddr_controller(void)
 	init_write_reg(MX6_IOM_DRAM_CAS, 0x00008030);
 	init_write_reg(MX6_IOM_DRAM_RAS, 0x00008030);
 	init_write_reg(MX6_IOM_GRP_ADDDS, 0x00000030);
-	init_write_reg(MX6_IOM_DRAM_RESET, 0x000C3030);
+	init_write_reg(MX6_IOM_DRAM_RESET, 0x00000030);
 	init_write_reg(MX6_IOM_DRAM_SDCKE0, 0x00003000);
 	init_write_reg(MX6_IOM_DRAM_SDCKE1, 0x00000000);
 	init_write_reg(MX6_IOM_DRAM_SDBA2, 0x00000000);
@@ -66,8 +66,8 @@ static void tqma6s_init_ddr_controller(void)
 	init_write_reg(MX6_IOM_GRP_B5DS, 0x00000000);
 	init_write_reg(MX6_IOM_GRP_B6DS, 0x00000000);
 	init_write_reg(MX6_IOM_GRP_B7DS, 0x00000000);
-	init_write_reg(MX6_IOM_DRAM_DQM0, 0x00000030);
 
+	init_write_reg(MX6_IOM_DRAM_DQM0, 0x00000030);
 	init_write_reg(MX6_IOM_DRAM_DQM1, 0x00000030);
 	init_write_reg(MX6_IOM_DRAM_DQM2, 0x00000030);
 	init_write_reg(MX6_IOM_DRAM_DQM3, 0x00000030);
@@ -80,17 +80,17 @@ static void tqma6s_init_ddr_controller(void)
 	/* memory interface calibration values */
 	init_write_reg(MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003);
 	init_write_reg(MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000);
-	init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E);
-	init_write_reg(MX6_MMDC_P0_MPWLDECTRL1, 0x00120014);
+	init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x004C004A);
+	init_write_reg(MX6_MMDC_P0_MPWLDECTRL1, 0x003F0048);
 	init_write_reg(MX6_MMDC_P1_MPWLDECTRL0, 0x00000000);
 	init_write_reg(MX6_MMDC_P1_MPWLDECTRL1, 0x00000000);
-	init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x0240023C);
-	init_write_reg(MX6_MMDC_P0_MPDGCTRL1, 0x0228022C);
+	init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x42440240);
+	init_write_reg(MX6_MMDC_P0_MPDGCTRL1, 0x022C022C);
 	init_write_reg(MX6_MMDC_P1_MPDGCTRL0, 0x00000000);
 	init_write_reg(MX6_MMDC_P1_MPDGCTRL1, 0x00000000);
-	init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A);
+	init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x484A504C);
 	init_write_reg(MX6_MMDC_P1_MPRDDLCTL, 0x00000000);
-	init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x36362A32);
+	init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x34322832);
 	init_write_reg(MX6_MMDC_P1_MPWRDLCTL, 0x00000000);
 	init_write_reg(MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333);
 	init_write_reg(MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333);
@@ -110,11 +110,12 @@ static void tqma6s_init_ddr_controller(void)
 	init_write_reg(MX6_MMDC_P0_MDCFG0, 0x3F435333);
 	init_write_reg(MX6_MMDC_P0_MDCFG1, 0xB68E8B63);
 	init_write_reg(MX6_MMDC_P0_MDCFG2, 0x01FF00DB);
-	init_write_reg(MX6_MMDC_P0_MDMISC, 0x00001740);
+	init_write_reg(MX6_MMDC_P0_MDMISC, 0x00011740);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000);
 
 	debug("spl: tqma6s MX6_MMDC_P0_MDSCR %x ....\n", __raw_readl(MX6_MMDC_P0_MDSCR));
 
+/* TODO: leave it in Power Up Default */
 	init_write_reg(MX6_MMDC_P0_MDRWD, 0x000026D2);
 	init_write_reg(MX6_MMDC_P0_MDOR, 0x00431023);
 	init_write_reg(MX6_MMDC_P0_MDASP, 0x00000017);
@@ -123,12 +124,12 @@ static void tqma6s_init_ddr_controller(void)
 	init_write_reg(MX6_MMDC_P0_MDCTL, 0x83190000);
 
 /* TODO: wait to CKE ???? */
-	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008032);
+	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00408032);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008033);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x00048031);
-	init_write_reg(MX6_MMDC_P0_MDSCR, 0x05208030);
+	init_write_reg(MX6_MMDC_P0_MDSCR, 0x15208030);
 	init_write_reg(MX6_MMDC_P0_MDSCR, 0x04008040);
-	init_write_reg(MX6_MMDC_P0_MDREF, 0x00005800);
+	init_write_reg(MX6_MMDC_P0_MDREF, 0x00007800);
 	init_write_reg(MX6_MMDC_P0_MPODTCTRL, 0x00022222);
 	init_write_reg(MX6_MMDC_P1_MPODTCTRL, 0x00000000);
 	init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002552D);