RISCV/RISCV64: Initialize cpuCycleTime_ps with arch.cpu_cycle_time_ps INI option

[PhilippvK]

Resolves Issue #98

Default/Fallback value: 32MHZ as this was used before. However base.ini and ETISS.ini currently default to 100MHz.

[PhilippvK]

The CI broke, but this is probably not related to my changes.

[rafzi]

I'd suggest to also change the value to 32k in base.ini, since that one is used in the default flow. Otherwise good to merge!

GNU savannah seems to be down, causing the CI failure.

[PhilippvK]

@rafzi I agree but we need to make this also clear in ETISS.ini which currently states:

  ; Set CPU freuquency in pico seconds
  ; (or1k)   default=10000
  ; (ARMv6M) default=31250

  arch.cpu_cycle_time_ps=10000

[github-actions]

Performance Statistics

Status for the gcc Just-In-Time Engine (for commit f77994d): No significant performance change
Current dhrystone MIPS for gcc JIT : 32.82
Previous best for gcc JIT (recorded in commit 08e5f28): 33.86, difference -3.08%

Status for the llvm Just-In-Time Engine (for commit f77994d): No significant performance change
Current dhrystone MIPS for llvm JIT : 20.84
Previous best for llvm JIT (recorded in commit 4a43dba): 21.52, difference -3.15%

Status for the tcc Just-In-Time Engine (for commit f77994d): No significant performance change
Current dhrystone MIPS for tcc JIT : 27.28
Previous best for tcc JIT (recorded in commit b27d7c4): 27.35, difference -0.29%

_{This comment was created automatically, please do not change!}