Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 * Fix subprojects that aren't tested from normal sims * Fix firechip for chisel 3.2.0 and rc bump * Bump boom for bug fix rebase * [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci] * Bump boom for rc bump fix to bug fix * Bump FireSim for CI check * Bump FireSim * Bump submodules after merge
ucb-bar · Dec 12, 2019 · 86a473d · 86a473d
1 parent c0564d3
commit 86a473d
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Showing 22 changed files with 36 additions and 33 deletions.
diff --git a/build.sbt b/build.sbt
@@ -7,14 +7,14 @@ lazy val chipyardRoot = RootProject(file("."))
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
   version := "1.0",
-  scalaVersion := "2.12.4",
+  scalaVersion := "2.12.10",
   traceLevel := 15,
   test in assembly := {},
   assemblyMergeStrategy in assembly := { _ match {
     case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
     case _ => MergeStrategy.first}},
   scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
-  libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.5" % "test",
+  libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.8" % "test",
   libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1",
   libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
   libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0",
@@ -35,7 +35,7 @@ lazy val firesimAsLibrary = sys.env.get("FIRESIM_STANDALONE") == None
 lazy val firesimDir = if (firesimAsLibrary) {
   file("sims/firesim/sim/")
 } else {
-  file("../../")
+  file("../../sim")
 }
 
 // Checks for -DROCKET_USE_MAVEN.
@@ -111,9 +111,12 @@ lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
 lazy val rocketMacros  = (project in rocketChipDir / "macros")
   .settings(commonSettings)
 
+lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
+  .settings(commonSettings)
+
 lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
   .settings(commonSettings)
-  .dependsOn(chisel, hardfloat, rocketMacros)
+  .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig)
 
 lazy val testchipip = (project in file("generators/testchipip"))
   .dependsOn(rocketchip)
@@ -181,15 +184,15 @@ lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
 
 lazy val sifive_cache = (project in file("generators/sifive-cache")).settings(
     commonSettings,
-    scalaSource in Compile := baseDirectory.value / "craft"
+    scalaSource in Compile := baseDirectory.value / "design/craft"
   ).dependsOn(rocketchip)
 
 // Library components of FireSim
 lazy val midas      = ProjectRef(firesimDir, "midas")
 lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
 
 lazy val firechip = (project in file("generators/firechip"))
-  .dependsOn(example, icenet, testchipip, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
+  .dependsOn(boom, hwacha, example, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
   .settings(
     commonSettings,
     testGrouping in Test := isolateAllTests( (definedTests in Test).value )

diff --git a/generators/boom b/generators/boom
diff --git a/generators/example/src/main/scala/Generator.scala b/generators/example/src/main/scala/Generator.scala
@@ -31,7 +31,7 @@ object Generator extends GeneratorApp {
   }
 
   // specify the name that the generator outputs files as
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
 
   // generate files
   generateFirrtl

diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala
@@ -30,7 +30,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
 
   val dut = p(BuildTop)(clock, reset.toBool, p)
 
-  dut.debug := DontCare
+  dut.debug.foreach(_ := DontCare)
   dut.connectSimAXIMem()
   dut.connectSimAXIMMIO()
   dut.dontTouchPorts()
@@ -65,7 +65,7 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
 
   val dut = p(BuildTopWithDTM)(clock, reset.toBool, p)
 
-  dut.reset := reset.asBool | dut.debug.ndreset
+  dut.reset := reset.asBool | dut.debug.get.ndreset
   dut.connectSimAXIMem()
   dut.connectSimAXIMMIO()
   dut.dontTouchPorts()
@@ -83,5 +83,5 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
     }
   })
 
-  Debug.connectDebug(dut.debug, clock, reset.asBool, io.success)
+  Debug.connectDebug(dut.debug, dut.psd, clock, reset.asBool, io.success)
 }
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -21,13 +21,13 @@ import firesim.util.RegisterBridgeBinder
 import tracegen.HasTraceGenTilesModuleImp
 
 class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
-  target.debug.clockeddmi.foreach({ cdmi =>
+  target.debug.foreach(_.clockeddmi.foreach({ cdmi =>
     cdmi.dmi.req.valid := false.B
     cdmi.dmi.req.bits := DontCare
     cdmi.dmi.resp.ready := false.B
     cdmi.dmiClock := false.B.asClock
     cdmi.dmiReset := false.B
-  })
+  }))
   Seq()
 })
 

diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala
@@ -4,7 +4,7 @@ package firesim.firesim
 
 import java.io.{File, FileWriter}
 
-import chisel3.experimental.RawModule
+import chisel3.RawModule
 import chisel3.internal.firrtl.{Circuit, Port}
 
 import freechips.rocketchip.diplomacy.{ValName, AutoBundle}
@@ -58,7 +58,7 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu
 }
 
 object FireSimGenerator extends App with IsFireSimGeneratorLike {
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   lazy val generatorArgs = GeneratorArgs(args)
   lazy val genDir = new File(names.targetDir)
   // The only reason this is not generateFirrtl; generateAnno is that we need to use a different 
@@ -70,7 +70,7 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike {
 
 // For now, provide a separate generator app when not specifically building for FireSim
 object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites {
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   generateFirrtl
   generateAnno
   generateTestSuiteMakefrags

diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -10,7 +10,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
-import freechips.rocketchip.devices.debug.DebugModuleParams
+import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
 import boom.common.BoomTilesKey
 import testchipip.{BlockDeviceKey, BlockDeviceConfig}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
@@ -77,7 +77,7 @@ class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
 
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
-  case DebugModuleParams => up(DebugModuleParams, site).copy(clockGate = false)
+  case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
 })
 
 // Testing configurations

diff --git a/generators/hwacha b/generators/hwacha
diff --git a/generators/icenet b/generators/icenet
diff --git a/generators/rocket-chip b/generators/rocket-chip
diff --git a/generators/sha3 b/generators/sha3
diff --git a/generators/sifive-blocks b/generators/sifive-blocks
diff --git a/generators/sifive-cache b/generators/sifive-cache
diff --git a/generators/testchipip b/generators/testchipip
diff --git a/generators/tracegen/src/main/scala/TestHarness.scala b/generators/tracegen/src/main/scala/TestHarness.scala
@@ -17,7 +17,7 @@ class TestHarness(implicit p: Parameters) extends Module {
 
 object Generator extends GeneratorApp {
   // specify the name that the generator outputs files as
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
 
   // generate files
   generateFirrtl

diff --git a/generators/utilities/src/main/scala/Subsystem.scala b/generators/utilities/src/main/scala/Subsystem.scala
@@ -66,7 +66,7 @@ trait HasBoomAndRocketTiles extends HasTiles
       def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocketLogicalTree.getOMInterruptTargets)
       LogicalModuleTree.add(logicalTreeNode, rocketLogicalTree)
 
-      connectInterrupts(tile, Some(debug), clintOpt, plicOpt)
+      connectInterrupts(tile, debugOpt, clintOpt, plicOpt)
 
       tile
     }

diff --git a/sims/firesim b/sims/firesim
diff --git a/tools/barstools b/tools/barstools
diff --git a/tools/chisel-testers b/tools/chisel-testers
diff --git a/tools/chisel3 b/tools/chisel3
diff --git a/tools/firrtl b/tools/firrtl
diff --git a/variables.mk b/variables.mk
@@ -140,7 +140,7 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M
 #########################################################################################
 # default sbt launch command
 #########################################################################################
-SCALA_VERSION=2.12.4
+SCALA_VERSION=2.12.10
 SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
 
 SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION)