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Failed to generate emulator with the latest master branch version #25
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I have encountered same problem when run make CONFIG=PWMConfig. |
It looks like this is me: riscvarchive/riscv-fesvr#25 There was a change to the way that arguments are exposed backwards from HTIF that changed this API. It looks like project template is using an older version of testchipip that's incompatible. I think that all that has to happen is a bump to testchipip. |
It looks like testchipip will also need modifications to its verilator-harness.cc. That could also benefit from an update to act like rocket-chip's emulator.cc. I may be able to look at this tomorrow. |
verilator-harness.cc has been revised for HTIF/FESVR API changes |
Hi, I clone the latest version from master branch at 2017.1.17.
Then I follow the README.md part to build emulator. However, it fails with some errors happen.
error message:
/project-template/testchipip/csrc/SimSerial.cc: In function ‘int serial_tick(unsigned char, unsigned char*, int, unsigned char*, unsigned char, int*)’:
/project-template/testchipip/csrc/SimSerial.cc:26:87: error: no matching function for call to ‘tsi_t::tsi_t(std::vector<std::basic_string >)’
tsi = new tsi_t(std::vectorstd::string(info.argv + 1, info.argv + info.argc));
^
/project-template/testchipip/csrc/SimSerial.cc:26:87: note: candidate is:
In file included from /project-template/testchipip/csrc/SimSerial.cc:5:0:
/project-template/rocket-chip/riscv-tools/include/fesvr/tsi.h:21:3: note: tsi_t::tsi_t(int, char**)
tsi_t(int argc, char** argv);
^
/project-template/rocket-chip/riscv-tools/include/fesvr/tsi.h:21:3: note: candidate expects 2 arguments, 1 provided
make[1]: *** [SimSerial.o] Error 1
make[1]: *** Waiting for unfinished jobs....
/project-template/testchipip/csrc/verilator-harness.cc: In function ‘int main(int, char**)’:
/project-template/testchipip/csrc/verilator-harness.cc:84:66: error: no matching function for call to ‘tsi_t::tsi_t(std::vector<std::basic_string >)’
tsi = new tsi_t(std::vectorstd::string(argv + 1, argv + argc));
^
/project-template/testchipip/csrc/verilator-harness.cc:84:66: note: candidate is:
In file included from /project-template/testchipip/csrc/verilator-harness.cc:7:0:
/project-template/rocket-chip/riscv-tools/include/fesvr/tsi.h:21:3: note: tsi_t::tsi_t(int, char**)
tsi_t(int argc, char** argv);
^
/project-template/rocket-chip/riscv-tools/include/fesvr/tsi.h:21:3: note: candidate expects 2 arguments, 1 provided
make[1]: *** [verilator-harness.o] Error 1
make[1]: Leaving directory `/project-template/verisim/generated-src/example.TestHarness.PWMConfig'
make: *** [/project-template/verisim/simulator-example-PWMConfig] Error 2
It seems the code verilator-harness.cc and SimSerial.cc in testchip/csrc exist some code syntax mismatch from riscv-tools/include/fesvr/tsi.h. I am not familiar with the section.
Could anyone helps me about it?
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