Spike-as-a-Tile #1307
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Spike-as-a-Tile #1307
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tianrui-wei
reviewed
Jan 7, 2023
tianrui-wei
reviewed
Jan 7, 2023
| val masterNode = visibilityNode | ||
| val slaveNode = TLIdentityNode() | ||
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| override def isaDTS = "rv64gcv_Zfh" |
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Is this true with the current CY toolchain?
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This isn't passed to the toolchain.
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I know it's not passed but right now we can't compile code outside gc right? I'm not sure it would make sense to restrict this to rv64gc for now.
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rv64gcv_Zfh is a superset of rv64gc. The cpu is always allowed to report that it has more capability than the software needs.
abejgonzalez
approved these changes
Jan 26, 2023
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Now that this exists, maybe it makes sense to boot Linux in CI with this. |
This needs a faster firemarshal linux image, |
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This PR integrates a spike processor model as a tile into chipyard.
The spike processor model supports any RISC-V ISA configuration Spike supports, and dynamically links with spike-as-a-library.
The spike processor interfaces with chipyard through a cache-coherent Tilelink model.
Of course, this shouldn't be used for any performance-modelling.
It is useful for stress-testing MMIO devices, or accelerators.
Adding RoCC support would be a cool extension.
Also, atomics aren't guaranteed to be atomic.
TODO:
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mainas the base branch?changelog:<topic>label?changelog:label?.conda-lock.ymlfile if you updated the conda requirements file?Please Backport?