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Small build system improvements #1349

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merged 4 commits into from
Feb 16, 2023
Merged

Small build system improvements #1349

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85fe061
Use EICG_wrapper model as addResource/Path | Fix Makefile parsing
abejgonzalez Feb 15, 2023
959cca6
Fix make help
abejgonzalez Feb 15, 2023
64bc8c1
Bump SBT to 1.8.2
abejgonzalez Feb 15, 2023
aa02295
Fix spacing of AbstactConfig
abejgonzalez Feb 16, 2023
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2 changes: 1 addition & 1 deletion common.mk
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Expand Up @@ -17,7 +17,7 @@ HELP_COMPILATION_VARIABLES += \
" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \
" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog) \
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \
" EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler"

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3 changes: 0 additions & 3 deletions fpga/Makefile
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Expand Up @@ -90,9 +90,6 @@ fpga_common_script_dir := $(fpga_dir)/common/tcl
#########################################################################################
# setup misc. sim files
#########################################################################################
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v

# copy files but ignore *.h files in *.f (match vcs)
$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR)
cp -f $^ $(OUT_DIR)
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1 change: 1 addition & 0 deletions generators/chipyard/src/main/scala/config/AbstractConfig.scala
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Expand Up @@ -51,6 +51,7 @@ class AbstractConfig extends Config(
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set)
new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus
new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
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2 changes: 1 addition & 1 deletion project/build.properties
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@@ -1 +1 @@
sbt.version=1.5.5
sbt.version=1.8.2
3 changes: 0 additions & 3 deletions sims/common-sim-flags.mk
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Expand Up @@ -33,6 +33,3 @@ SIM_LDFLAGS = \
-lfesvr \
-ldramsim \
$(EXTRA_SIM_LDFLAGS)

SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
3 changes: 1 addition & 2 deletions vlsi/Makefile
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Expand Up @@ -54,7 +54,7 @@ endif
#########################################################################################
# general rules
#########################################################################################
.PHONY: default
.PHONY: default all
default: all

all: drc lvs
Expand Down Expand Up @@ -82,7 +82,6 @@ ifneq ($(CUSTOM_VLOG), )
else
cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL)
echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL)
endif

#########################################################################################
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