Fix Verilog Prerequisites + Ignore mv stdout

[abejgonzalez]

• Fixes issue where if you updated a Verilog file, the SFC_LEVEL would be not set breaking the flow. Done by moving the VLOG_SOURCES as a prereq of SFC_LEVEL.
• Adds new ibex.mk so that if a Ibex file is updated it would elaborate the SoC again (which would preprocess the Verilog sources)
• Ignores mv stderr output (the error code is ignored anyways by using -)
• xcelium support #1386 never passed CI. This fixes 2 errors with the PR, not init'ing the DramSim submodule and changing the int to size_t in cospike/spiketile.cc so that GCC can detect that the cfg_t constructor is valid.

Related PRs / Issues:
Requires review on ucb-bar/ibex-wrapper#5

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

[joonho3020]

LGTM pending CI