Update NoC example config to match new PRCI organization

[jerryz123]

NoC node mapping needs to be updated to match the new PRCI bus organization.

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

[joonho3020]

MultiNoCConfig is fixed, but SharedNoCConfig results in the same error.

[jerryz123]

MultiNoCConfig is fixed, but SharedNoCConfig results in the same error.

I'm not able to reproduce an error for SharedNoC... can you post the error?

[joonho3020]

/ecad/tools/synopsys/fm/current/bin
/ecad/tools/mentor/calibre/current/bin
/ecad/tools/synopsys/verdi/current/bin
/ecad/tools/cadence/XCELIUM/current/tools/bin/64bit
/ecad/tools/cadence/XCELIUM/current/tools/bin
/scratch/joonho.whangbo/coding/pandoc-2.19.2/bin
/scratch/joonho.whangbo/clangd_16.0.2/bin
/home/eecs/joonho.whangbo/.local/share/coursier/bin
Exception in thread "main" java.lang.reflect.InvocationTargetException
	at ... ()
	at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:36)
	at ... ()
	at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
Caused by: java.lang.IllegalArgumentException: advance1(1073741824, 2147483616): a1=[Ljava.lang.Object;@16f839ef, a2=[[Ljava.lang.Object;@64a46a3d, a3=[[[Ljava.lang.Object;@2629e469, a4=[[[[Ljava.lang.Object;@62582eb8, a5=[[[[[Ljava.lang.Object;@3538445d, a6=[[[[[[Ljava.lang.Object;@728a2545, depth=6
	at scala.collection.immutable.VectorBuilder.advance1(Vector.scala:1657)
	at scala.collection.immutable.VectorBuilder.advance(Vector.scala:1612)
	at scala.collection.immutable.VectorBuilder.addArr1(Vector.scala:1572)
	at scala.collection.immutable.VectorBuilder.addVector(Vector.scala:1591)
	at scala.collection.immutable.VectorBuilder.addAll(Vector.scala:1602)
	at scala.collection.immutable.VectorBuilder.addAll(Vector.scala:1388)
	at scala.collection.StrictOptimizedIterableOps.flatMap(StrictOptimizedIterableOps.scala:118)
	at scala.collection.StrictOptimizedIterableOps.flatMap$(StrictOptimizedIterableOps.scala:105)
	at scala.collection.immutable.Vector.flatMap(Vector.scala:113)
	at chisel3.util.experimental.decode.QMCMinimizer$.$anonfun$getCover$7(QMCMinimizer.scala:212)
	at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
	at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
	at scala.collection.immutable.List.foldLeft(List.scala:79)
	at chisel3.util.experimental.decode.QMCMinimizer$.getCover(QMCMinimizer.scala:212)
	at chisel3.util.experimental.decode.QMCMinimizer$.$anonfun$minimize$12(QMCMinimizer.scala:302)
	at chisel3.util.experimental.decode.QMCMinimizer$.$anonfun$minimize$12$adapted(QMCMinimizer.scala:244)
	at scala.collection.StrictOptimizedIterableOps.flatMap(StrictOptimizedIterableOps.scala:118)
	at scala.collection.StrictOptimizedIterableOps.flatMap$(StrictOptimizedIterableOps.scala:105)
	at scala.collection.immutable.Range.flatMap(Range.scala:59)
	at chisel3.util.experimental.decode.QMCMinimizer$.minimize(QMCMinimizer.scala:244)
	at chisel3.util.experimental.decode.decoder$.$anonfun$apply$1(decoder.scala:25)
	at scala.collection.immutable.Map$EmptyMap$.getOrElse(Map.scala:226)
	at chisel3.util.experimental.decode.decoder$.apply(decoder.scala:25)
	at chisel3.util.experimental.decode.decoder$.qmc(decoder.scala:59)
	at chisel3.util.experimental.decode.decoder$.qmcFallBack$1(decoder.scala:74)
	at chisel3.util.experimental.decode.decoder$.apply(decoder.scala:81)
	at constellation.router.RouteComputer.$anonfun$new$15(RouteComputer.scala:81)
	at chisel3.internal.prefix$.apply(prefix.scala:48)
	at constellation.router.RouteComputer.$anonfun$new$14(RouteComputer.scala:76)
	at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
	at constellation.router.RouteComputer.$anonfun$new$1(RouteComputer.scala:45)
	at constellation.router.RouteComputer.$anonfun$new$1$adapted(RouteComputer.scala:45)
	at scala.collection.immutable.Vector1.map(Vector.scala:1925)
	at scala.collection.immutable.Vector1.map(Vector.scala:377)
	at constellation.router.RouteComputer.<init>(RouteComputer.scala:45)
	at constellation.router.Router$$anon$1.$anonfun$route_computer$2(Router.scala:134)
	at chisel3.Module$.do_apply(Module.scala:53)
	at constellation.router.Router$$anon$1.$anonfun$route_computer$1(Router.scala:134)
	at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
	at constellation.router.Router$$anon$1.<init>(Router.scala:134)
	at constellation.router.Router.$anonfun$module$1(Router.scala:89)
	at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
	at constellation.router.Router.module$lzycompute(Router.scala:89)
	at constellation.router.Router.module(Router.scala:89)
	at constellation.router.Router.module(Router.scala:67)
	at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$15(LazyModule.scala:334)
	at chisel3.Module$.do_apply(Module.scala:53)
	at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$14(LazyModule.scala:334)
	at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
	at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$13(LazyModule.scala:334)
	at scala.Option.getOrElse(Option.scala:201)
	at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:332)
	at scala.collection.immutable.List.flatMap(List.scala:293)
	at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:308)
	at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:305)
	at freechips.rocketchip.diplomacy.LazyRawModuleImp.instantiate(LazyModule.scala:401)
	at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$2(LazyModule.scala:414)
	at chisel3.withClockAndReset$.apply(MultiClock.scala:26)
	at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$1(LazyModule.scala:414)
	at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48)
	at freechips.rocketchip.diplomacy.LazyRawModuleImp.<init>(LazyModule.scala:413)
	at freechips.rocketchip.prci.Domain$Impl.<init>(ClockDomain.scala:11)
	at freechips.rocketchip.prci.Domain.$anonfun$module$1(ClockDomain.scala:10)
	at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
	at freechips.rocketchip.prci.Domain.module$lzycompute(ClockDomain.scala:10)
	at freechips.rocketchip.prci.Domain.module(ClockDomain.scala:10)

Error looks like this. Maybe there is some scala-level recursion problem in constellation when computing routing tables?

[jerryz123]

Does it always fail like this? This looks like a bug in the chisel QMC minimizer.

[jerryz123]

I'll merge this for now

[joonho3020]

Yeah, it fails like this... Okay sounds good

[joonho3020]

@abejgonzalez Can you try building the SharedNoCConfig (just to check if I'm crazy)?

[abejgonzalez]

I can successfully run both configs to Verilog generation with this PR merged in.

[joonho3020]

Hmm.. thanks!