Improve QoR for Log2

For reasonable circuit delay, need to divide & conquer.
chipsalliance · Jul 7, 2016 · c90be4e · c90be4e
1 parent a49e27d
commit c90be4e
Showing 1 changed file with 9 additions and 1 deletion.
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -19,10 +19,18 @@ object Log2 {
       UInt(0)
     } else if (width == 2) {
       x(1)
-    } else {
+    } else if (width <= divideAndConquerThreshold) {
       Mux(x(width-1), UInt(width-1), apply(x, width-1))
+    } else {
+      val mid = 1 << (log2Ceil(width) - 1)
+      val hi = x(width-1, mid)
+      val lo = x(mid-1, 0)
+      val useHi = hi.orR
+      Cat(useHi, Mux(useHi, Log2(hi, width - mid), Log2(lo, mid)))
     }
   }
 
   def apply(x: Bits): UInt = apply(x, x.getWidth)
+
+  private def divideAndConquerThreshold = 4
 }