IDWT 5x3 single-pass lifting and SSE2/AVX2 implementation #957
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Implements #953
With the new bench_dwt utility, on x86_64:
SSE2/AVX2 is used in the vertical pass to handle several columns at the same time. This avoids a lot of CPU cache trashing.
Note: I tried a SSE2 optimized version of opj_idwt53_h_cas0() but the gain is almost unnoticeable, so not included in this PR.