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1. SYN_FIFO_UVM SYN_FIFO_UVM Public

   A UVM based testbench for the synchronous FIFO.

   SystemVerilog 3 1

2. SYN_SRAM_UVM SYN_SRAM_UVM Public

   A UVM based testbench for a synchronous static RAM.

   SystemVerilog 1

3. UART_UVM UART_UVM Public

   A testbench for UART using UVM

   SystemVerilog 1