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imx8mp-var-dart: add support for DART-MX8M-PLUS 2.0
Update the default device trees to support MXL86110 ethernet PHY and NXP IW612 Wi-Fi/BT module on DART-MX8M-PLUS 2.0. Add legacy support for 1.x DART-MX8M-PLUS module. Signed-off-by: Alifer Moraes <alifer.m@variscite.com>
1 parent 53a0580 commit 17b1593

10 files changed

+455
-364
lines changed

‎arch/arm64/boot/dts/freescale/Makefile

Lines changed: 2 additions & 1 deletion
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@@ -76,7 +76,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.d
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb imx8mp-var-som-symphony-2nd-ov5640.dtb \
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imx8mp-var-som-1.x-symphony.dtb imx8mp-var-som-1.x-symphony-2nd-ov5640.dtb \
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imx8mp-var-dart-dt8mcustomboard.dtb imx8mp-var-dart-dt8mcustomboard-legacy.dtb
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imx8mp-var-dart-dt8mcustomboard.dtb imx8mp-var-dart-dt8mcustomboard-legacy.dtb \
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imx8mp-var-dart-1.x-dt8mcustomboard.dtb imx8mp-var-dart-1.x-dt8mcustomboard-legacy.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \
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imx8mq-evk-usdhc2-m2.dtb imx8mq-evk-pcie-ep.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-ak4497.dtb imx8mq-evk-audio-tdm.dtb imx8mq-evk-pdm.dtb

‎arch/arm64/boot/dts/freescale/imx8mp-var-dart-1.x-dt8mcustomboard-legacy.dts

Lines changed: 11 additions & 0 deletions
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@@ -0,0 +1,11 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2024 Variscite Ltd.
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*/
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#include "imx8mp-var-dart-1.x.dtsi"
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#include "imx8mp-var-dart-dt8mcustomboard-legacy.dtsi"
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/ {
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model = "Variscite DART-MX8M-PLUS v1.x on DT8MCustomBoard 1.x";
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};

‎arch/arm64/boot/dts/freescale/imx8mp-var-dart-1.x-dt8mcustomboard.dts

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@@ -0,0 +1,11 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* 2024 Variscite Ltd.
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*/
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#include "imx8mp-var-dart-1.x.dtsi"
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#include "imx8mp-var-dart-dt8mcustomboard.dtsi"
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/ {
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model = "Variscite DART-MX8M-PLUS v1.x on DT8MCustomBoard 2.x and above";
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};

‎arch/arm64/boot/dts/freescale/imx8mp-var-dart-1.x.dtsi

Lines changed: 30 additions & 0 deletions
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@@ -0,0 +1,30 @@
1+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device tree overlay to support the DART-MX8M-PLUS 1.x
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*
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* Copyright 2024 Variscite Ltd.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx8mp-var-dart.dtsi"
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&iw612_pwrseq {
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status = "disabled";
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};
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&reg_eqos_phy {
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gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
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};
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/* WIFI */
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&usdhc1 {
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mmc-pwrseq = <>;
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brcmf: bcrmf@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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laird,regdomain = "US";
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};
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};

‎arch/arm64/boot/dts/freescale/imx8mp-var-dart-dt8mcustomboard-common.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
4-
* Copyright 2020-2021 Variscite Ltd.
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* Copyright 2020-2024 Variscite Ltd.
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*/
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/ {

‎arch/arm64/boot/dts/freescale/imx8mp-var-dart-dt8mcustomboard-legacy.dts

Lines changed: 3 additions & 171 deletions
Original file line numberDiff line numberDiff line change
@@ -1,180 +1,12 @@
11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
22
/*
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* Copyright 2019 NXP
4-
* Copyright 2020-2021 Variscite Ltd.
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* Copyright 2020-2024 Variscite Ltd.
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*/
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#include "imx8mp-var-dart.dtsi"
8-
#include "imx8mp-var-dart-dt8mcustomboard-common.dtsi"
8+
#include "imx8mp-var-dart-dt8mcustomboard-legacy.dtsi"
99

1010
/ {
11-
model = "Variscite DART-MX8M-PLUS on DT8MCustomBoard 1.x";
12-
13-
gpio-keys {
14-
pinctrl-names = "default";
15-
pinctrl-0 = <&pinctrl_gpio_keys>;
16-
17-
up {
18-
gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
19-
};
20-
21-
down {
22-
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
23-
};
24-
25-
home {
26-
gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
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};
28-
29-
back {
30-
gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
31-
};
32-
};
33-
34-
leds {
35-
emmc {
36-
gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
37-
};
38-
};
39-
40-
can0_osc: can0_osc {
41-
clock-frequency = <20000000>;
42-
};
43-
};
44-
45-
&i2c2 {
46-
ov5640_mipi0: ov5640_mipi@3c {
47-
pinctrl-names = "default";
48-
pinctrl-0 = <&pinctrl_csi0>;
49-
powerdown-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
50-
reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
51-
};
52-
53-
ft5x06_ts: ft5x06_ts@38 {
54-
reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
55-
};
56-
57-
/* USB Type-C Controller */
58-
extcon_ptn5150: typec@3d {
59-
compatible = "nxp,ptn5150";
60-
pinctrl-names = "default";
61-
pinctrl-0 = <&pinctrl_extcon>;
62-
reg = <0x3d>;
63-
int-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
64-
status ="okay";
65-
};
66-
};
67-
68-
&i2c4 {
69-
ov5640_mipi1: ov5640_mipi@3c {
70-
pinctrl-names = "default";
71-
pinctrl-0 = <&pinctrl_csi1>;
72-
powerdown-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
73-
reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
74-
};
75-
};
76-
77-
&pcie {
78-
pinctrl-names = "default";
79-
pinctrl-0 = <&pinctrl_pcie>;
80-
reset-gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
81-
};
82-
83-
&usb_dwc3_0 {
84-
extcon = <&extcon_ptn5150>;
85-
};
86-
87-
&can0 {
88-
spi-max-frequency = <10000000>;
89-
};
90-
91-
&gpio1 {
92-
pinctrl-names = "default";
93-
pinctrl-0 = <&pinctrl_hdmi>;
94-
95-
hdmi_on_hog {
96-
gpio-hog;
97-
gpios = <5 0>;
98-
output-low;
99-
line-name = "hdmi_on";
100-
};
101-
};
102-
103-
&iomuxc {
104-
pinctrl_flexcan1: flexcan1grp {
105-
fsl,pins = <
106-
MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
107-
MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
108-
>;
109-
};
110-
111-
pinctrl_flexcan2: flexcan2grp {
112-
fsl,pins = <
113-
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
114-
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
115-
>;
116-
};
117-
118-
pinctrl_captouch: captouchgrp {
119-
fsl,pins = <
120-
MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x1c6
121-
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x16
122-
>;
123-
};
124-
125-
pinctrl_extcon: extcongrp {
126-
fsl,pins = <
127-
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19
128-
>;
129-
};
130-
131-
pinctrl_can: cangrp {
132-
fsl,pins = <
133-
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x1c6
134-
>;
135-
};
136-
137-
pinctrl_csi0: csi0grp {
138-
fsl,pins = <
139-
MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x19
140-
MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x19
141-
>;
142-
};
143-
144-
pinctrl_pcie: pciegrp {
145-
fsl,pins = <
146-
MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x41
147-
>;
148-
};
149-
150-
pinctrl_csi1: csi1grp {
151-
fsl,pins = <
152-
MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x19
153-
MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x19
154-
>;
155-
};
156-
157-
pinctrl_hdmi: hdmigrp {
158-
fsl,pins = <
159-
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0xc1
160-
>;
161-
};
162-
163-
pinctrl_gpio_keys: keygrp {
164-
fsl,pins = <
165-
MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x143
166-
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x143
167-
MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x143
168-
MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x143
169-
>;
170-
};
171-
172-
pinctrl_gpio_leds: ledgrp {
173-
fsl,pins = <
174-
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0xc6
175-
MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0xc6
176-
MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0xc6
177-
MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0xc6
178-
>;
179-
};
11+
model = "Variscite DART-MX8M-PLUS v2.x on DT8MCustomBoard 1.x";
18012
};

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