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| 1 | +* MaxLinear MXL8611x PHY Device Tree binding |
| 2 | + |
| 3 | +Required properties: |
| 4 | +- reg: PHY address |
| 5 | + |
| 6 | +Optional properties: |
| 7 | +- mxl-8611x,ledN_cfg: Register configuration for COM_EXT_LED0_CFG, |
| 8 | + COM_EXT_LED1_CFG, and COM_EXT_LED2_CFG |
| 9 | +- mxl-8611x,rx-internal-delay-ps: RGMII RX Clock Delay used only when PHY operates |
| 10 | + in RGMII mode with internal delay (phy-mode is 'rgmii-id' or |
| 11 | + 'rgmii-rxid') in pico-seconds. |
| 12 | +- mxl-8611x,tx-internal-delay-ps-100m: RGMII TX Clock Delay used only when PHY operates |
| 13 | + in 10/100M RGMII mode with internal delay (phy-mode is 'rgmii-id' or |
| 14 | + 'rgmii-txid') in pico-seconds. |
| 15 | +- mxl-8611x,tx-internal-delay-ps-1g: RGMII TX Clock Delay used only when PHY operates |
| 16 | + in 1G RGMII mode with internal delay (phy-mode is 'rgmii-id' or |
| 17 | + 'rgmii-txid') in pico-seconds. |
| 18 | + |
| 19 | +Example: |
| 20 | + |
| 21 | + ethernet-phy@0 { |
| 22 | + reg = <0>; |
| 23 | + |
| 24 | + mxl-8611x,led0_cfg = <( |
| 25 | + MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON | |
| 26 | + MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON | |
| 27 | + MXL8611X_LEDX_CFG_TRAFFIC_ACT_BLINK_IND |
| 28 | + )>; |
| 29 | + mxl-8611x,led1_cfg = <( |
| 30 | + MXL8611X_LEDX_CFG_LINK_UP_10MB_ON | |
| 31 | + MXL8611X_LEDX_CFG_LINK_UP_100MB_ON | |
| 32 | + MXL8611X_LEDX_CFG_LINK_UP_1GB_ON |
| 33 | + )>; |
| 34 | + mxl-8611x,rx-internal-delay-ps = <0>; |
| 35 | + mxl-8611x,tx-internal-delay-ps-100m = <2250>; |
| 36 | + mxl-8611x,tx-internal-delay-ps-1g = <150>; |
| 37 | + }; |
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