SystemVerilog preprocessor, lexer and parser with examples
The preprocessor was inspired by the excellent mcpp by Kiyoshi Matsui.
The lexer and parser are based on the IEEE spec.
Any questions I had with the spec are marked // FRED in IEEE1800_2017Parser.g4.
This project is designed so that it can used with Project Scandium.
The files in src/org are from The ANTRL Project and are covered by ANTLR_LICENSE. Other files and ANTLR modifications are covered by LICENSE.
Type make
Use ./demo.sh <SystemVerilog filename(s)>
The Example program:
- Runs the preprocessor and checks if any `define's are left defined.
- Runs the lexer and parser. Optionally pretty-prints the parse tree.
- Runs an example linter.
- Extracts and prints module headers.
The project was built on:
Oracle Linux Server release 9.4
using:
java 22.0.1 2024-04-16
Java(TM) SE Runtime Environment (build 22.0.1+8-16)
Java HotSpot(TM) 64-Bit Server VM (build 22.0.1+8-16, mixed mode, sharing)
- ANTLR ANother Tool for Language Recognition. BSD-3-clause license
- MCPP A portable C preprocessor. BSD-2-clause license
- 2.0.0 Update Antlr version and add CI.
- 1.0.1 Use curl instead of wget (for macOS)
- 1.0.0 Initial Release