Unsupported: little endian ordering for arrays

[phantom-killua]

Verilator version

Verilator 4.038 2020-07-11 rev v4.036-114-g0cd4a57ad

Testcase

typedef struct packed {
  logic [9:0] a;
} t1;

typedef struct packed {
  logic [6:0] b;
  /* verilator lint_off LITENDIAN */
  t1 [0:4] c;
  /* verilator lint_on LITENDIAN */
  logic d;
} t2;

/* verilator lint_off DECLFILENAME */
module our;
/* verilator lint_on DECLFILENAME */
  t2 t;
  initial begin
    //1111111 1000010000 1000011000 1000011100 1000011110 1000011111 0
    assign t = 58'b1111111100001000010000110001000011100100001111010000111110; 
    $displayb(t.b);
    $displayb(t.c[0].a);
    $displayb(t.d);
    $finish;
  end
endmodule

Simulation Result

1111111
1000011111
0
- t/t_little_endian_err.v:25: Verilog $finish

I think the value of "t.c[0].a" is 1000010000, not 1000011111, Because c ("t1 [0:4] c;") is little endian. I think it's a bug, What do you all think?

[wsnyder]

Confirmed, needs some effort to fix, if you or someone has time a pull request for a fix would be appreciated.

As the array can be seen via a "different" mechanism all bits must be reversed. This is annoying and once fixed will greatly slow down any code using little endian, but I don't see an alternative. Yet another reason to not use little endian ;)