Wrong value read from little-endian array

[atorregrosa-smd]

Verilator version:
4.108 (issue appears after fix for #2499)

Testcase

module top;
   initial begin
      logic [0:4][31:0] test  = '{0, 1, 2, 3, 4};
      logic [4:0][31:0] test2 = test;

      $display(test[1]);
      $display(test2[1]);
      $finish;
   end
endmodule

Verilator displays values 3,1, when other simulators show the correct sequence 1,3. Older Verilator versions showed 1,1 which is also wrong.

I'll be glad to submit a fix if you give me some guidance.

[wsnyder]

Thanks for the report and offer to fix, simple enough so just fixed it, had lo/hi instead of left/right.