Adding failing test case for source synchronous signals

[dpetrisko]

Source-synchronous structs are a common construct. With complex code, Verilator does not detect the clock signal in the struct as a clock. Trying to fix this with a clocker pragma results in the following error, exposed by this test case:

======================================================================
vlt/t_source_sync: ==================================================
        perl /home/dpetrisko/scratch/verilator/test_regress/../bin/verilator --prefix Vt_source_sync ../obj_vlt/t_source_sync/Vt_source_sync__main.cpp --exe --make gmake --x-assign unique -cc -Mdir obj_vlt/t_source_sync -OD --debug-check --comp-limit-members 10 --clk clk  -f input.vc +define+TEST_OBJ_DIR=obj_vlt/t_source_sync t/t_source_sync.v    > obj_vlt/t_source_sync/vlt_compile.log
%Error: t/t_source_sync.v:20:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';'
   20 |    logic clk /*verilator clocker*/ ;
      |              ^~~~~~~~~~~~~~~~~~~~~
%Error: t/t_source_sync.v:22:1: syntax error, unexpected '}'
   22 | } ss_s;
      | ^
%Error: Exiting due to 2 error(s)
%Warning: vlt/t_source_sync: Exec of perl failed: %Error: t/t_source_sync.v:20:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';'

vlt/t_source_sync: %Error: Exec of perl failed: %Error: t/t_source_sync.v:20:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';'
vlt/t_source_sync: FAILED: Exec of perl failed: %Error: t/t_source_sync.v:20:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';'
==SUMMARY: Passed 0  Failed 1  Unsup 0  Time 0:01
==SUMMARY: Passed 0  Failed 1  Unsup 0  Time 0:01

======================================================================
        #vlt/t_source_sync: %Error: Exec of perl failed: %Error: t/t_source_sync.v:20:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';'
                make && test_regress/t/t_source_sync.pl  --vlt
TESTS DONE, FAILED: Passed 0  Failed 1  Unsup 0  Time 0:01

[dpetrisko]

Let me know if you would like me to raise an issue for tracking as well!

[wsnyder]

Could you please change the .pl file to indicate a failure is expected? Then we can merge the test as failing (incorrectly due to #3047). When #3047 is fixed the .pl file would be edited to indicate it should pass.

Thanks.

[wsnyder]

I think the test should somehow check that the clocker attribute is honored.

[dpetrisko]

Yeah I was having trouble with that. Basically the problem was that Verilator is normally good about inferring the source synchronous signal for small designs. Only my large complex design suddenly started having problems (always_ff @(s.clk) not triggering, etc.)

So when I wrote a test that actually exercised this, it spuriously passed

[dpetrisko]

Could you please change the .pl file to indicate a failure is expected?

Done!

[wsnyder]

Please see the test failure - maybe need to update .out?

[dpetrisko]

Yep, there was a whitespace issue on the .out file, sorry about that. Should be good to go now!