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Adding failing test case for source synchronous signals #3038
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%Error: t/t_source_sync.v:8:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';' | ||
8 | logic clk /*verilator clocker*/ ; | ||
| ^~~~~~~~~~~~~~~~~~~~~ | ||
%Error: t/t_source_sync.v:10:1: syntax error, unexpected '}' | ||
10 | } ss_s; | ||
| ^ | ||
%Error: Exiting due to |
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#!/usr/bin/env perl | ||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
# | ||
# Copyright 2019 by Wilson Snyder. This program is free software; you | ||
# can redistribute it and/or modify it under the terms of either the GNU | ||
# Lesser General Public License Version 3 or the Perl Artistic License | ||
# Version 2.0. | ||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
|
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scenarios(vlt => 1); | ||
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compile( | ||
fails => 1, | ||
expect_filename => $Self->{golden_filename}, | ||
); | ||
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ok(1); | ||
1; |
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// DESCRIPTION: Verilator: Verilog Test module | ||
// | ||
// This file ONLY is placed under the Creative Commons Public Domain, for | ||
// any use, without warranty, 2020 by Dan Petrisko. | ||
// SPDX-License-Identifier: CC0-1.0 | ||
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typedef struct packed { | ||
logic clk /*verilator clocker*/; | ||
logic data; | ||
} ss_s; | ||
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endmodule | ||
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I think the test should somehow check that the clocker attribute is honored.
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Yeah I was having trouble with that. Basically the problem was that Verilator is normally good about inferring the source synchronous signal for small designs. Only my large complex design suddenly started having problems (always_ff @(s.clk) not triggering, etc.)
So when I wrote a test that actually exercised this, it spuriously passed