GitHub - viraj-dhanushka/Verilog-based-CPU: A 32-bit CPU which includes an ALU, a Register File, Control Unit, Data and Instruction memory

How to Use:

Compile (make sure filles.txt is in the directory) iverilog -o my_design.vvp -c filles.txt
Run vvp my_design.vvp
Open with gtkwave tool gtkwave cpu_wavedata.vcd

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Procedure		Procedure
README.md		README.md
alu.v		alu.v
and_gate.v		and_gate.v
assembler.c		assembler.c
branch_check.v		branch_check.v
control_unit.v		control_unit.v
cpu.v		cpu.v
cpu_tb.v		cpu_tb.v
data_cache.v		data_cache.v
data_memory.v		data_memory.v
datapath.v		datapath.v
decoder.v		decoder.v
filles.txt		filles.txt
instruction_cache.v		instruction_cache.v
instruction_memory.v		instruction_memory.v
mux.v		mux.v
mux_read_instcache.v		mux_read_instcache.v
mux_readdata.v		mux_readdata.v
new_adder.v		new_adder.v
or_gate.v		or_gate.v
pc_unit.v		pc_unit.v
reg_file.v		reg_file.v
signextend.v		signextend.v
twos_complement.v		twos_complement.v