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nodejs: Fix PowerPC CPU detection and codegen to work with more processors. #62
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added 2 commits
February 19, 2022 18:35
Update Node.js package version to 16.14.0.
This patch defines the correct optional Power ISA features that the PPC code generator needs in order to run without crashing on v2.01 and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more efficiently on CPUs with features that weren't being used before. PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions, and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit to/from double, as well as integer to/from single-precision float. Use the current PPC_5_PLUS CPU feature to determine whether to generate FP round to int, and use the PPC_7_PLUS feature to determine whether to use the v2.06 ISA instructions or whether to generate an alternate generic PPC sequence to handle the cases of 64-bit unsigned integer to/from floating point, integers to single-precision floating point, and loading and storing 64-bit integers with byte reversal. Add a new PPC_7_PLUS_NXP feature for the popcnt and ldbrx/stdbrx opcodes added in Power ISA v2.06, which are also present in the NXP e5500 and e6500 cores, which are otherwise missing many of the features added since v2.01. This enables NXP cores to use a few more features. Additionally, bring back the ISELECT feature flag, which is also supported by NXP cores, including older ones, and has its own AT_HWCAP2 feature flag in Linux. By defining a new ICACHE_SNOOP feature bit to replace the use of PPC_6_PLUS, the meaning of the instruction cache flushing fast path, and the CPUs that can use it, is more clearly defined. In addition, for the other PowerPC chips, the loop to flush the data and instruction cache blocks has been split into two loops, with a single "sync" and "isync" after each loop, which should be more efficient, and also handles the few CPUs with differing data and instruction cache line sizes. In the macro assembler methods, in addition to providing an alternate path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary instructions to move sp down and then immediately back up were replaced with negative offsets from the current sp. This should be faster, and also sp is supposed to point to a back chain at all times (V8 may not do this).
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does this supersede the other PR? |
The other patch is for "nodejs-lts" (v12) and this patch is for "nodejs" (v16, the latest stable branch). I needed to get Node.js LTS working to build Firefox and I thought it would be helpful to patch this as well. I'm going to work on getting these patches upstreamed into the V8 repo. |
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ah, i see, gotcha |
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btw, as it is this does not build on musl, need some fallbacks for missing hwcap constants: https://github.com/void-linux/void-packages/blob/master/srcpkgs/nodejs/patches/xxx-ppc-hwcap-musl.patch (you should consider that when upstreaming this) |
josegpt
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Mar 2, 2022
This patch defines the correct optional Power ISA features that the PPC code generator needs in order to run without crashing on v2.01 and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more efficiently on CPUs with features that weren't being used before. PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions, and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit to/from double, as well as integer to/from single-precision float. Use the current PPC_5_PLUS CPU feature to determine whether to generate FP round to int, and use the PPC_7_PLUS feature to determine whether to use the v2.06 ISA instructions or whether to generate an alternate generic PPC sequence to handle the cases of 64-bit unsigned integer to/from floating point, integers to single-precision floating point, and loading and storing 64-bit integers with byte reversal. Add a new PPC_7_PLUS_NXP feature for the popcnt and ldbrx/stdbrx opcodes added in Power ISA v2.06, which are also present in the NXP e5500 and e6500 cores, which are otherwise missing many of the features added since v2.01. This enables NXP cores to use a few more features. Additionally, bring back the ISELECT feature flag, which is also supported by NXP cores, including older ones, and has its own AT_HWCAP2 feature flag in Linux. By defining a new ICACHE_SNOOP feature bit to replace the use of PPC_6_PLUS, the meaning of the instruction cache flushing fast path, and the CPUs that can use it, is more clearly defined. In addition, for the other PowerPC chips, the loop to flush the data and instruction cache blocks has been split into two loops, with a single "sync" and "isync" after each loop, which should be more efficient, and also handles the few CPUs with differing data and instruction cache line sizes. In the macro assembler methods, in addition to providing an alternate path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary instructions to move sp down and then immediately back up were replaced with negative offsets from the current sp. This should be faster, and also sp is supposed to point to a back chain at all times (V8 may not do this). Closes void-ppc#62
gmbeard
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Mar 12, 2022
This patch defines the correct optional Power ISA features that the PPC code generator needs in order to run without crashing on v2.01 and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more efficiently on CPUs with features that weren't being used before. PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions, and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit to/from double, as well as integer to/from single-precision float. Use the current PPC_5_PLUS CPU feature to determine whether to generate FP round to int, and use the PPC_7_PLUS feature to determine whether to use the v2.06 ISA instructions or whether to generate an alternate generic PPC sequence to handle the cases of 64-bit unsigned integer to/from floating point, integers to single-precision floating point, and loading and storing 64-bit integers with byte reversal. Add a new PPC_7_PLUS_NXP feature for the popcnt and ldbrx/stdbrx opcodes added in Power ISA v2.06, which are also present in the NXP e5500 and e6500 cores, which are otherwise missing many of the features added since v2.01. This enables NXP cores to use a few more features. Additionally, bring back the ISELECT feature flag, which is also supported by NXP cores, including older ones, and has its own AT_HWCAP2 feature flag in Linux. By defining a new ICACHE_SNOOP feature bit to replace the use of PPC_6_PLUS, the meaning of the instruction cache flushing fast path, and the CPUs that can use it, is more clearly defined. In addition, for the other PowerPC chips, the loop to flush the data and instruction cache blocks has been split into two loops, with a single "sync" and "isync" after each loop, which should be more efficient, and also handles the few CPUs with differing data and instruction cache line sizes. In the macro assembler methods, in addition to providing an alternate path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary instructions to move sp down and then immediately back up were replaced with negative offsets from the current sp. This should be faster, and also sp is supposed to point to a back chain at all times (V8 may not do this). Closes void-ppc#62
algor512
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Mar 13, 2022
This patch defines the correct optional Power ISA features that the PPC code generator needs in order to run without crashing on v2.01 and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more efficiently on CPUs with features that weren't being used before. PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions, and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit to/from double, as well as integer to/from single-precision float. Use the current PPC_5_PLUS CPU feature to determine whether to generate FP round to int, and use the PPC_7_PLUS feature to determine whether to use the v2.06 ISA instructions or whether to generate an alternate generic PPC sequence to handle the cases of 64-bit unsigned integer to/from floating point, integers to single-precision floating point, and loading and storing 64-bit integers with byte reversal. Add a new PPC_7_PLUS_NXP feature for the popcnt and ldbrx/stdbrx opcodes added in Power ISA v2.06, which are also present in the NXP e5500 and e6500 cores, which are otherwise missing many of the features added since v2.01. This enables NXP cores to use a few more features. Additionally, bring back the ISELECT feature flag, which is also supported by NXP cores, including older ones, and has its own AT_HWCAP2 feature flag in Linux. By defining a new ICACHE_SNOOP feature bit to replace the use of PPC_6_PLUS, the meaning of the instruction cache flushing fast path, and the CPUs that can use it, is more clearly defined. In addition, for the other PowerPC chips, the loop to flush the data and instruction cache blocks has been split into two loops, with a single "sync" and "isync" after each loop, which should be more efficient, and also handles the few CPUs with differing data and instruction cache line sizes. In the macro assembler methods, in addition to providing an alternate path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary instructions to move sp down and then immediately back up were replaced with negative offsets from the current sp. This should be faster, and also sp is supposed to point to a back chain at all times (V8 may not do this). Closes void-ppc#62
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Updated Node.js version from 16.13.2 to 16.14.0 and added a new patch to fix JIT code generation for pre-POWER7 CPUs, including G5 PowerMac and NXP e5500/e6500. This patch will unblock anyone who needs Node.js to work on a G5, e.g. to build Firefox, and it shouldn't affect POWER7 and newer at all.
Testing the changes
Local build testing