CSR changes for Vector extension

[stevobailey]

The following CSR registers in the CPU probably need to be changed to properly flag having a vector extension. See the privileged spec:

1. Machine ISA register, misa, bit 21 should be set
2. Machine status register, mstatus, VS bits 10:9, should be used as vector status bits

There may be others. Note that setting the VS bits in the mstatus register were required to get simulation working with spike. I'm not sure what hardware is supposed to do with the VS bits.

[michael-platzer]

Yes, indeed, these flags are not implemented yet. The V extension specification requires that "Attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when mstatus.VS is set to Off." Hence, spike requires the VS bits but since this functionality is still missing Vicuna does not.

Also, the vector byte length vlenb CSR is still missing. The other vector CSR registers required by the V extension are currently supported when using Ibex as the main core (but not for CV32E40X).

I am working on several changes to the handling of the vector CSRs. I will keep this issue open as a reminder to add the missing flags and registers.