🙂
This space always under construction !
Open to collaboration for
1) ASIC/SoC/FPGA RTL design & Verification
2) Embedded Systems
3) DSP, CV, DS and ML
4) Comp Architecture, Digital Comm
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UVM_Tutorial_Udemy_Coursework
UVM_Tutorial_Udemy_Coursework Publiccoursework on OVM and UVM by Udemy
SystemVerilog 1
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verification
verification PublicThis repository is my shot at SV and UVM for basic Design & Verification data structures
SystemVerilog 2
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