Help wanted: Testing with Nexys4 DDR (or Nexys A7-100T) appreciated

[wfjm]

The w11a design for Nexys4 DDR, see rtl/sys_gen/w11a/nexys4d, was provided to support also an up-to-date Nexys4 board. It is so far only simulation tested.

Testing done with a real Nexyx4 DDR, or a newer Nexys A7-100T, would be highly appreciated. Please double check the pin assignments (see mig_a.prj and nexys4d*.xdc) with the documentation of your board to avoid potential damage.

Looking forward to receive test reports.

[wfjm]

The Nexys4 (classic, with 16 MByte PSRAM) board on which most of the recent w11 was done broke in late July 2019 (see blog) and a Nexys A7 was ordered as replacement.

Basic tests with the test designs sys_tst_serloop2 and sys_tst_rlink_n4d and the BRAM-only w11 design sys_w11a_br_n4d worked fine.

But all tests involving the DDR2 memory interface failed. The culprit was quickly found, it was a mistake in the MIG configuration mig_a.prj, the polarity of the SYS_RST signal was ACTIVE LOW instead of ACTIVE HIGH. After fixing this, the test designs sys_tst_mig_n4d and sys_tst_sram_n4d as well as the w11 implementation sys_w11a_n4d worked right away.

The tst_sram designs show nicely that the DDR2 on the Nexys A7 board is slightly slower than the DDR3 on the Arty A7 board

   Board     test time   clock period     UI_CLK
  Nexys A7     37.36 s        3333 ps   75.0 MHz 
  Arty A7      35.77 s        3000 ps   83.3 MHz

The issue is closed with commit 563e230.