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21 Open 29 Closed
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Issues list

Automated generation of mutiple registers for width > 32
#68 opened May 5, 2024 by wzab
Explicit register addresses as constants in HDL package
#66 opened Dec 11, 2023 by lepommosaure
4
Potential problem with constants within block declarations.
#63 opened Apr 13, 2021 by m-kru
Better handling of BlackBoxes - support for HLS?
#61 opened Mar 17, 2021 by wzab
9
Connecting Wishbone busses - naming conventions
#60 opened Feb 21, 2021 by wzab
Selection between "agwb" and "agwb_dca" does not work correctly now.
#57 opened Feb 7, 2021 by wzab
1
Implementation of the "extended interface" - to make use of the extended features of IPbus, E2bus or CBM DCA - how to implement RMW?
#55 opened Feb 2, 2021 by wzab
3
Current CDC block is inefficient for connecting clock domains using synchronous clocks with different frequencies
#54 opened Jan 27, 2021 by wzab
Generation of multiple AGWB tree instances to be used in the same design
#45 opened Dec 20, 2020 by wzab
1
Add regression testing.
#44 opened Dec 18, 2020 by m-kru
Split code into packages and modules.
#43 opened Dec 18, 2020 by m-kru
Treating subblock elements as a block instantiation.
#42 opened Dec 18, 2020 by m-kru
Port name for aggregated outputs does not follow the naming convention.
#40 opened Nov 26, 2020 by m-kru
@m-kru
Add description for math within value attributes in the docs.
#38 opened Nov 26, 2020 by m-kru
@wzab
Document base parameter for agwb.Block class
#33 opened Nov 5, 2020 by m-kru
C++ backend - how to enable run-time resolution of addresses
#30 opened Oct 28, 2020 by wzab
In the HTML documentation the length of object (blocks or register) vectors is not shown
#24 opened Dec 30, 2019 by wzab
Improved handling of blackboxes
#22 opened Sep 10, 2019 by wzab
Error announced by xwb_crossbar, when the block contains only a blackbox.
#16 opened Jul 19, 2019 by wzab
All t_*2stlv() functions return std_logic_vector of length 32.
#11 opened Apr 14, 2019 by m-kru
Option to define active reset value.
#9 opened Apr 11, 2019 by m-kru
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