8x8 Fused-Multiply-Add (FMA) Unit

A 8x8 FMA unit was generated using Pyrilog and tested on DE1-SOC board.

The unit first generates all the partial products from each multiplication, and places all of them into a giant Wallace Partial Product Reduction Tree (PPRT) so that the results can be computed in a single cycle.

The code to test the implementation on hardware (exhaustively) can be found in src/software/main.c under the grid_test_8x8 method. A recursive implementation is done so that all elements of the dot product can be tested. This is left running for a prolonged period of time while I figure out how to migrate this project onto Vivado, and eventually on Amazon AWS F1 instance.

8x8 Tree Multiplier

A functional implementation of a 8-bit tree multiplier.

The multiplier makes use of the Baugh-Wooley method to handle compensating for negative weighted bits in the signed multiplication. The partial products are reduced using a Wallace tree.

Note

This project was regenerated from scratch from a previous implementation which got too messy and out of hand. Therefore the first git tag created here seems very sudden.