Improve detection of multiply declared signals in SV frontend

[azonenberg]

Feature Description

The current Verilog frontend does not detect cases where a signal is declared multiple times with conflicting types (often the result of changing an internal net to be a module port, but not deleting the original declaration).

Example:

module foo(input wire bar);

logic bar; //should warn but does not currently

endmodule

#3817 will detect multiple drivers if the "logic" signal is initialized while also being declared as a module port, but it seems like we should still consider this code "wrong" even if the "logic" version of bar is never explicitly driven.

[nakengelhardt]

Only compatible declarations should pass this block, so now that conflicts with constant drivers are better detected in check this should only accept relatively "harmless" mistakes, but maybe someone can figure out how to add some checks on the declaration there.