Suboptimal default synthesis of $bmux, $shiftx

[povik]

Version

Yosys 0.31+45 (git sha1 7212397, clang 11.1.0 -fPIC -Os)

On which OS did this happen?

macOS

Reproduction Steps

Working on #3880 I noticed $bmux and $shiftx are mapped onto gates suboptimally by the default synthesis script. The mapping does not make use of undef bits.

Consider the following example, where we have instances of bmux and shiftx which we synthesize with techmap; abc; (modelling what synth does, producing equivalent result here) and separately with techmap; opt_expr -mux_undef; abc.

read_verilog -icells <<EOF
module shiftx(input [9:0] data, input [5:0] sel, output [1:0] out);
	$shiftx #(
		.A_WIDTH(10),
		.A_SIGNED(0),
		.B_WIDTH(6),
		.B_SIGNED(0),
		.Y_WIDTH(2),
	) shiftx(
		.A(data),
		.B(sel),
		.Y(out)
	);
endmodule

module bmux(input [5:0] data, input [5:0] sel, output [2:0] out);
	$bmux #(
		.S_WIDTH(6),
		.WIDTH(3)
	) bmux(
		.A({{186{1'bx}}, data}),
		.S(sel),
		.Y(out)
	);
endmodule
EOF

copy bmux bmux2
copy shiftx shiftx2

select bmux shiftx
techmap; abc

select bmux2 shiftx2
techmap; opt_expr -mux_undef; abc

select -clear
stat

Expected Behavior

The default synthesis script makes full use of the undef bits for reduced gate count.

Actual Behavior

There's a gate count gap between what techmap; abc; (equivalent to synth here) and techmap; opt_expr -mux_undef; abc; produce. As far as I can tell ABC has no concept of undef bits, and when Yosys hands over the circuit it replaces all instances of undef bits with zero. With explicit insertion of opt_expr -mux_undef the undef bits are exploited to eliminate some of the muxes.

The FPGA scripts I looked into (at least synth_ice40) don't seem to suffer from the same thing because they happen to call opt_expr -mux_undef ahead of abc in the map_ffs block.

Output from the script above:

=== bmux ===

   Number of wires:                 10
   Number of wire bits:             22
   Number of public wires:           3
   Number of public wire bits:      15
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $_ANDNOT_                       1
     $_AND_                          4
     $_MUX_                          3
     $_NOR_                          2

=== bmux2 ===

   Number of wires:                  3
   Number of wire bits:             15
   Number of public wires:           3
   Number of public wire bits:      15
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  3
     $_MUX_                          3

=== shiftx ===

   Number of wires:                 25
   Number of wire bits:             40
   Number of public wires:           3
   Number of public wire bits:      18
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 24
     $_ANDNOT_                       3
     $_MUX_                         15
     $_NAND_                         4
     $_ORNOT_                        2

=== shiftx2 ===

   Number of wires:                 18
   Number of wire bits:             33
   Number of public wires:           3
   Number of public wire bits:      18
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 17
     $_MUX_                         17

[povik]

Similar: #878