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crash in select and delete #4082

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oharboe opened this issue Dec 19, 2023 · 1 comment · Fixed by #4118
Closed

crash in select and delete #4082

oharboe opened this issue Dec 19, 2023 · 1 comment · Fixed by #4118
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@oharboe
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oharboe commented Dec 19, 2023

Version

Yosys 0.33 (git sha1 2584903, gcc 13.2.0-4ubuntu3 -fPIC -Os)

On which OS did this happen?

Linux

Reproduction Steps

Using:

module cc_banks_8192x64(
  input  [12:0] RW0_addr,
  input         RW0_en,
                RW0_clk,
                RW0_wmode,
  input  [63:0] RW0_wdata,
  output [63:0] RW0_rdata
);

  reg [63:0] Memory[0:8191];
  reg [12:0] _RW0_raddr_d0;
  reg        _RW0_ren_d0;
  reg        _RW0_rmode_d0;
  always @(posedge RW0_clk) begin
    _RW0_raddr_d0 <= RW0_addr;
    _RW0_ren_d0 <= RW0_en;
    _RW0_rmode_d0 <= RW0_wmode;
    if (RW0_en & RW0_wmode)
      Memory[RW0_addr] <= RW0_wdata;
  end // always @(posedge)
  assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx;
endmodule
yosys

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.33 (git sha1 2584903a0, gcc 13.2.0-4ubuntu3 -fPIC -Os)


yosys> read_verilog designs/src/harness/cc_banks_8192x64.sv 
1. Executing Verilog-2005 frontend: designs/src/harness/cc_banks_8192x64.sv
Parsing Verilog input from `designs/src/harness/cc_banks_8192x64.sv' to AST representation.
Generating RTLIL representation for module `\cc_banks_8192x64'.
Successfully finished Verilog frontend.

yosys> select cc_banks_8192x64/w:* cc_banks_8192x64/c:*

yosys*> select -del cc_banks_8192x64/i:* cc_banks_8192x64:o:*
Warning: Selection "cc_banks_8192x64:o:*" did not match any module.

yosys*> select -del cc_banks_8192x64/i:* cc_banks_8192x64/o:*

yosys*> delete
ERROR: Assert `!it.first.has_const()' failed in kernel/rtlil.cc:1950.

Expected Behavior

No crash

Actual Behavior

crash

@oharboe oharboe added the pending-verification This issue is pending verification and/or reproduction label Dec 19, 2023
@oharboe
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oharboe commented Dec 19, 2023

Also happens in Yosys 0.36 (git sha1 8f07a0d84, gcc 13.2.0-4ubuntu3 -fPIC -Os)

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