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Yosys Verilog Parsing Error: Unable to Synthesize After Reading File #4427
Comments
Changing lines 31 and 32 to the following makes it compile fine: reg289[(3'h6):(3'h5)] : {"Q",
($unsigned((8'hb6)) ? "t" : "e")})); Looking at the source where the assert is being raised it seems to be a problem with the parsing of string constants: |
If a `RTLIL::Const` is composed of multiple strings, such as when using a ternary expression to select between two strings of different lengths, zero padding for the strings needs to be maintained. Only leading (and trailing) null characters should be dropped from the decoded string, rather than all null characters.
Minimal example (for the error): module top ();
wire [15:0] x = {"1", "\0"};
endmodule
|
Version
yosys 0.41+126
On which OS did this happen?
Linux
Reproduction Steps
Hello,
I encountered an error while using Yosys to read a Verilog file. The steps and the error message are as follows:
After this error, the parsing process is interrupted. I have checked the Verilog file for syntax errors but couldn't find any obvious issues. I am using the latest version of Yosys.
Attached is the Verilog file (design.v) that triggers the error.
Thank you in advance for your attention to this matter.
I look forward to hearing from you regarding this issue.
design_file.zip
Expected Behavior
synthesis success
Actual Behavior
synthesis fail
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