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ARM Assembly
Shuai YUAN edited this page Nov 8, 2023
·
2 revisions
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pre-indexed address mode
STR
-
post-indexed address mode
LDR
.data
var1: .word 3
var2: .word 4
.text
.global _start
_start:
ldr r0, adr_var1 @ load the memory address of var1 via label adr_var1 to R0
ldr r1, adr_var2 @ load the memory address of var2 via label adr_var2 to R1
ldr r2, [r0] @ load the value (0x03) at memory address found in R0 to R2
str r2, [r1, r2, LSL#2] @ address mode: offset. Store the value found in R2 (0x03) to the memory address found in R1 with the offset R2 left-shifted by 2. Base register (R1) unmodified.
str r2, [r1, r2, LSL#2]! @ address mode: pre-indexed. Store the value found in R2 (0x03) to the memory address found in R1 with the offset R2 left-shifted by 2. Base register modified: R1 = R1 + R2<<2
ldr r3, [r1], r2, LSL#2 @ address mode: post-indexed. Load value at memory address found in R1 to the register R3. Then modifiy base register: R1 = R1 + R2<<2
bkpt
adr_var1: .word var1
adr_var2: .word var2
.section .text
.global _start
_start:
ldr r0, =jump /* load the address of the function label jump into R0 */
ldr r1, =0x68DB00AD /* load the value 0x68DB00AD into R1 */
jump:
ldr r2, =511 /* load the value 511 into R2 */
bkpt
- immediate value
v
:v = n ror 2*r
,n
8-bit,r
4-bit. - ways to bypass this restrictions:
- Construct a larger value out of smaller parts
- Instead of using
MOV r0, #511
- Split 511 into two parts:
MOV r0, #256
, andADD r0, #255
- Use a load construct ‘ldr r1,=value’ which the assembler will happily convert into a
MOV
, or a PC-relative load if that is not possible.
LDR r1, =511
-
LDM
/STM
variations:-IA
(increase after),-IB
(increase before),-DA
(decrease after),-DB
(decrease before) -
PUSH
is a synonym forSTMDB sp!
- the address in
SP
gets DECREASED by 4. - information gets stored to the new address pointed by
SP
.
- the address in
-
POP
is a synonym forLDMIA sp!
- The value at the current
SP
address is loaded into a certain register, - Address in
SP
gets INCREASED by 4.
- The value at the current