Pinned Loading

1. uvm_tb_cross_bar uvm_tb_cross_bar Public

   SystemVerilog UVM testbench example

   SystemVerilog 27 10

2. system_console system_console Public

   Tcl packages for Quartus Prime System Console(FPGA debugging).

   Tcl 3

3. color_questasim color_questasim Public

   A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

   Perl 4

4. quartus_cadence_netlist_merger quartus_cadence_netlist_merger Public

   Quartus pin and Cadence Allegro net-list merger

   Python 3 1

5. eda-scripts eda-scripts Public

   Collection of scripts for EDA tools

   Shell 6 2

6. allegro-configs allegro-configs Public

   My configuration files for Cadence/Allegro

   Common Lisp 6 2