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  1. sv2v Public

    SystemVerilog to Verilog conversion

    Haskell 197 29

  2. Yosys Open SYnthesis Suite

    C++ 1.9k 553

466 contributions in the last year

Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Mon Wed Fri

Contribution activity

September 2021

Created 1 repository
Opened 2 pull requests in 1 repository
Reviewed 3 pull requests in 2 repositories

Created an issue in steveicarus/iverilog that received 2 comments

inaccurate combination if signedness of non-ANSI style port declarations

Per 23.2.2.1 of IEEE 1800-2017: The signed attribute can be attached either to a port declaration or the corresponding net or variable declaration…

2 comments
1 contribution in private repositories Sep 10

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