zachjs
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February 2021
Created 36 commits in 2 repositories
Created a pull request in YosysHQ/yosys that received 3 comments
verilog: error on macro invocations with missing argument lists
This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly …
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Opened 10 other pull requests in 1 repository
YosysHQ/yosys
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7
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- genrtlil: improve name conflict error messaging
- Extend simplify() recursion warning
- verilog: fix handling of nested ifdef directives
- Fix double-free on unmatched logger error pattern
- verilog: fix sizing of constant args for tasks/functions
- verilog: support recursive functions using ternary expressions
- Set aside extraneous tests in simple_abc9 test suite
- verlog: allow shadowing module ports within generate blocks
- genrtlil: fix signed port connection codegen failures
- verilog: refactored constant function evaluation
Reviewed 9 pull requests in 1 repository
YosysHQ/yosys 9 pull requests
- Add $countbits, $countones, $isunknown, $onehot and $onehot0 functions
- Fix handling of unique/unique0/priority cases in the frontend.
- Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off
- Fix syntax error in adff2dff.v
- frontend: Make helper functions for printing locations.
- Adds is_wire to SigBit and SigChunk
- verilog_parser: fix missing is_signed attribute in type_atom
- Add loop iterator declaration in the loop definition
- verilog_parser: add label check to gen_block
Created an issue in steveicarus/iverilog that received 4 comments
$bits on item in a generate block fails when used in a constant expression
module top; parameter ENABLE = 1; if (ENABLE) begin : blk wire [7:0] w; end wire [7:0] x; wire [$bits(blk.w)-1:0] y; wire [$bits(x)-1:0] z; ini…
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