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  1. SystemVerilog to Verilog conversion

    Haskell 150 18

  2. Yosys Open SYnthesis Suite

    C++ 1.6k 492

360 contributions in the last year

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Contribution activity

February 2021

Created 36 commits in 2 repositories

Created a pull request in YosysHQ/yosys that received 3 comments

verilog: error on macro invocations with missing argument lists

This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly …

+32 −1 3 comments

Created an issue in steveicarus/iverilog that received 4 comments

$bits on item in a generate block fails when used in a constant expression

module top; parameter ENABLE = 1; if (ENABLE) begin : blk wire [7:0] w; end wire [7:0] x; wire [$bits(blk.w)-1:0] y; wire [$bits(x)-1:0] z; ini…

4 comments

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