Skip to content

Commit 7f40908

Browse files
msierszulskicarlescufi
msierszulski
authored and
carlescufi
committed
soc: silabs_exx32: Add support for SiLabs efr32mg24 SoC
This commit adds support for Silicon Labs EFR32MG24 SoC. Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
1 parent 491f274 commit 7f40908

File tree

9 files changed

+341
-0
lines changed

9 files changed

+341
-0
lines changed

‎dts/arm/silabs/efr32mg24-pinctrl.dtsi

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/*
2+
* Copyright (c) 2022 Silicon Labs
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <dt-bindings/pinctrl/gecko-pinctrl.h>
8+
9+
&pinctrl {
10+
/* configuration for uart0 device, default state */
11+
usart0_default: usart0_default {
12+
group1 {
13+
/* configure PA.6 as UART_RX and PA.5 as UART_TX */
14+
psels = <GECKO_PSEL(UART_TX, A, 5)>,
15+
<GECKO_PSEL(UART_RX, A, 6)>,
16+
<GECKO_LOC(UART, 0)>;
17+
};
18+
};
19+
};

‎dts/arm/silabs/efr32mg24.dtsi

Lines changed: 169 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,169 @@
1+
/*
2+
* Copyright (c) 2020 TriaGnoSys GmbH
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <arm/armv8-m.dtsi>
8+
#include <dt-bindings/gpio/gpio.h>
9+
#include <arm/silabs/gpio_gecko.h>
10+
#include <dt-bindings/i2c/i2c.h>
11+
#include <dt-bindings/pinctrl/gecko-pinctrl.h>
12+
13+
/ {
14+
chosen {
15+
zephyr,flash-controller = &msc;
16+
zephyr,entropy = &trng;
17+
};
18+
19+
cpus {
20+
#address-cells = <1>;
21+
#size-cells = <0>;
22+
23+
cpu0: cpu@0 {
24+
device_type = "cpu";
25+
compatible = "arm,cortex-m33";
26+
reg = <0>;
27+
cpu-power-states = <&state0>;
28+
};
29+
};
30+
31+
power-states {
32+
state0: state0 {
33+
compatible = "zephyr,power-state";
34+
power-state-name = "standby";
35+
min-residency-us = <50000>;
36+
exit-latency-us = <0>;
37+
};
38+
};
39+
40+
sram0: memory@20000000 {
41+
device_type = "memory";
42+
compatible = "mmio-sram";
43+
};
44+
45+
soc {
46+
msc: flash-controller@50030000 {
47+
compatible = "silabs,gecko-flash-controller";
48+
reg = <0x50030000 0x3148>;
49+
interrupts = <50 0>;
50+
51+
#address-cells = <1>;
52+
#size-cells = <1>;
53+
54+
flash0: flash@0 {
55+
compatible = "soc-nv-flash";
56+
write-block-size = <4>;
57+
erase-block-size = <8192>;
58+
};
59+
};
60+
61+
usart0: usart@5005c000 {
62+
compatible = "silabs,gecko-usart";
63+
reg = <0x5005C000 0x306c>;
64+
interrupts = <9 0>, <10 0>;
65+
interrupt-names = "rx", "tx";
66+
peripheral-id = <0>;
67+
status = "disabled";
68+
};
69+
70+
trng: trng@5c021000 {
71+
compatible = "silabs,gecko-trng";
72+
reg = < 0x5C021000 0x1000 >;
73+
status = "disabled";
74+
interrupts = < 0x1 0x0 >;
75+
};
76+
77+
stimer0: stimer@500a8000 {
78+
compatible = "silabs,gecko-stimer";
79+
reg = <0x500a8000 0x3054>;
80+
interrupts = <67 0>;
81+
clock-frequency = <32768>;
82+
prescaler = <1>;
83+
status = "disabled";
84+
};
85+
86+
gpio: gpio@5003c000 {
87+
compatible = "silabs,gecko-gpio";
88+
reg = <0x5003c000 0x4000>;
89+
interrupts = <26 2>, <25 2>;
90+
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
91+
92+
ranges;
93+
#address-cells = <1>;
94+
#size-cells = <1>;
95+
96+
gpioa: gpio@5003c030 {
97+
compatible = "silabs,gecko-gpio-port";
98+
reg = <0x5003c030 0x30>;
99+
peripheral-id = <0>;
100+
gpio-controller;
101+
#gpio-cells = <2>;
102+
status = "disabled";
103+
};
104+
105+
gpiob: gpio@5003c060 {
106+
compatible = "silabs,gecko-gpio-port";
107+
reg = <0x5003c060 0x30>;
108+
peripheral-id = <1>;
109+
gpio-controller;
110+
#gpio-cells = <2>;
111+
status = "disabled";
112+
};
113+
114+
gpioc: gpio@5003c090 {
115+
compatible = "silabs,gecko-gpio-port";
116+
reg = <0x5003c090 0x30>;
117+
peripheral-id = <2>;
118+
gpio-controller;
119+
#gpio-cells = <2>;
120+
status = "disabled";
121+
};
122+
123+
gpiod: gpio@5003c0C0 {
124+
compatible = "silabs,gecko-gpio-port";
125+
reg = <0x5003c0C0 0x30>;
126+
peripheral-id = <3>;
127+
gpio-controller;
128+
#gpio-cells = <2>;
129+
status = "disabled";
130+
};
131+
};
132+
133+
wdog0: wdog@5b004000 {
134+
compatible = "silabs,gecko-wdog";
135+
reg = <0x5b004000 0x2C>;
136+
peripheral-id = <0>;
137+
interrupts = <42 0>;
138+
status = "disabled";
139+
};
140+
141+
wdog1: wdog@5b008000 {
142+
compatible = "silabs,gecko-wdog";
143+
reg = <0x5b008000 0x2C>;
144+
peripheral-id = <1>;
145+
interrupts = <43 0>;
146+
status = "disabled";
147+
};
148+
};
149+
};
150+
151+
/ {
152+
pinctrl: pin-controller {
153+
/* Pin controller is a "virtual" device since SiLabs SoCs do pin
154+
* control in a distributed way (GPIO registers and PSEL
155+
* registers on each peripheral).
156+
*/
157+
compatible = "silabs,gecko-pinctrl";
158+
};
159+
160+
hwinfo: hwinfo {
161+
compatible = "silabs,gecko-hwinfo";
162+
status = "disabled";
163+
};
164+
165+
};
166+
167+
&nvic {
168+
arm,num-irq-priority-bits = <4>;
169+
};

‎dts/arm/silabs/efr32mg24b310f1536im48.dtsi

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
/*
2+
* Copyright (c) 2019 Steven Lemaire
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <mem.h>
8+
#include <silabs/efr32mg24.dtsi>
9+
10+
/ {
11+
sram0: memory@20000000 {
12+
reg = <0x20000000 DT_SIZE_K(256)>;
13+
};
14+
15+
soc {
16+
compatible = "silabs,efr32mg24b310f1536im48",
17+
"silabs,efr32mg24", "silabs,efr32",
18+
"simple-bus";
19+
20+
flash-controller@50030000 {
21+
flash0: flash@0 {
22+
reg = <0 DT_SIZE_K(1536)>;
23+
};
24+
};
25+
};
26+
};

‎soc/arm/silabs_exx32/efr32mg24/Kconfig.defconfig.series

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
# Silicon Labs EFR32MG24 (Mighty Gecko) MCU configuration options
2+
3+
# Copyright (c) 2021 Sateesh Kotapati
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
if SOC_SERIES_EFR32MG24
7+
8+
config SOC_SERIES
9+
default "efr32mg24"
10+
11+
config SOC_PART_NUMBER
12+
default "EFR32MG24B310F1536IM48" if SOC_PART_NUMBER_EFR32MG24B310F1536IM48
13+
14+
config NUM_IRQS
15+
# must be >= the highest interrupt number used
16+
default 75
17+
18+
config PM
19+
default n
20+
21+
choice PM_POLICY
22+
default PM_POLICY_DEFAULT
23+
depends on PM
24+
endchoice
25+
26+
endif # SOC_SERIES_EFR32MG24

‎soc/arm/silabs_exx32/efr32mg24/Kconfig.series

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
# Silicon Labs EFR32MG24 (Mighty Gecko) MCU
2+
3+
# Copyright (c) 2021 Sateesh Kotapati
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
config SOC_SERIES_EFR32MG24
7+
bool "EFR32MG24 Series MCU"
8+
select ARM
9+
select CPU_CORTEX_M33
10+
select CPU_HAS_FPU
11+
select CPU_HAS_ARM_MPU
12+
select CPU_HAS_ARM_SAU
13+
select CPU_CORTEX_M_HAS_DWT
14+
select ARMV8_M_DSP
15+
select ARM_TRUSTZONE_M
16+
select SOC_FAMILY_EXX32
17+
select HAS_SILABS_GECKO
18+
select HAS_SWO
19+
select SOC_GECKO_CMU
20+
select SOC_GECKO_EMU
21+
select SOC_GECKO_GPIO
22+
select SOC_GECKO_DEV_INIT
23+
select COUNTER_GECKO_STIMER
24+
help
25+
Enable support for EFR32MG24 Mighty Gecko MCU series

‎soc/arm/silabs_exx32/efr32mg24/Kconfig.soc

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
# Silicon Labs EFR32MG24 (Mighty Gecko) MCU line
2+
3+
# Copyright (c) 2020 TriaGnoSys GmbH
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
config SOC_PART_NUMBER_EFR32MG24B310F1536IM48
7+
bool
8+
depends on SOC_SERIES_EFR32MG24

‎soc/arm/silabs_exx32/efr32mg24/linker.ld

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
/*
2+
* Copyright (c) 2021 Sateesh Kotapati
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/**
8+
* @file
9+
* @brief Linker command/script file
10+
*
11+
* This is the linker script for both standard images.
12+
*/
13+
14+
#include <autoconf.h>
15+
16+
#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

‎soc/arm/silabs_exx32/efr32mg24/soc.h

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
/*
2+
* Copyright (c) 2020 TriaGnoSys GmbH
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/**
8+
* @file
9+
* @brief Board configuration macros for the EFR32MG24 SoC
10+
*
11+
*/
12+
13+
#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_H
14+
#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_H
15+
16+
#include <zephyr/sys/util.h>
17+
18+
#ifndef _ASMLANGUAGE
19+
20+
#include <em_common.h>
21+
22+
#include "soc_pinmap.h"
23+
#include "../common/soc_gpio.h"
24+
25+
/* Add include for DTS generated information */
26+
#include <zephyr/devicetree.h>
27+
28+
#endif /* !_ASMLANGUAGE */
29+
30+
#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_H */

‎soc/arm/silabs_exx32/efr32mg24/soc_pinmap.h

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
/*
2+
* Copyright (c) 2020 TriaGnoSys GmbH
3+
* SPDX-License-Identifier: Apache-2.0
4+
*/
5+
6+
/** @file
7+
* @brief Silabs EFR32MG24 MCU pin definitions.
8+
*
9+
* This file contains pin configuration data required by different MCU
10+
* modules to correctly configure GPIO controller.
11+
*/
12+
13+
#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_PINMAP_H_
14+
#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_PINMAP_H_
15+
16+
#include <em_gpio.h>
17+
18+
#ifdef CONFIG_LOG_BACKEND_SWO
19+
#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 }
20+
#endif /* CONFIG_LOG_BACKEND_SWO */
21+
22+
#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_PINMAP_H_ */

0 commit comments

Comments
 (0)