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nandojvembolivar-nordic
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drivers: clock: Add Atmel SAM PMC driver
Add initial version of clock control for Atmel SAM SoC series. This add support to Power Management which allows control peripherals clock. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
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‎drivers/clock_control/CMakeLists.txt

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@@ -21,6 +21,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_cont
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1 clock_control_ifx_cat1.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM clock_control_sam_pmc.c)
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if(CONFIG_CLOCK_CONTROL_STM32_CUBE)

‎drivers/clock_control/Kconfig

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@@ -68,4 +68,6 @@ source "drivers/clock_control/Kconfig.aspeed"
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source "drivers/clock_control/Kconfig.gd32"
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source "drivers/clock_control/Kconfig.sam"
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endif # CLOCK_CONTROL

‎drivers/clock_control/Kconfig.sam

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# Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_SAM
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bool "Atmel SAM clock control"
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default y
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depends on DT_HAS_ATMEL_SAM_PMC_ENABLED
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help
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Enable driver for Atmel SAM Clock Control.

‎drivers/clock_control/clock_control_sam_pmc.c

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/*
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* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam_pmc
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#include <stdint.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
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static int atmel_sam_clock_control_on(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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const struct atmel_sam_pmc_config *cfg = (const struct atmel_sam_pmc_config *)sys;
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if (cfg == NULL) {
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LOG_ERR("The PMC config can not be NULL.");
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return -ENXIO;
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}
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LOG_DBG("Type: %x, Id: %d", cfg->clock_type, cfg->peripheral_id);
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switch (cfg->clock_type) {
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case PMC_TYPE_PERIPHERAL:
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soc_pmc_peripheral_enable(cfg->peripheral_id);
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break;
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default:
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LOG_ERR("The PMC clock type is not implemented.");
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return -ENODEV;
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}
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return 0;
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}
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static int atmel_sam_clock_control_off(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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const struct atmel_sam_pmc_config *cfg = (const struct atmel_sam_pmc_config *)sys;
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if (cfg == NULL) {
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LOG_ERR("The PMC config can not be NULL.");
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return -ENXIO;
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}
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LOG_DBG("Type: %x, Id: %d", cfg->clock_type, cfg->peripheral_id);
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switch (cfg->clock_type) {
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case PMC_TYPE_PERIPHERAL:
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soc_pmc_peripheral_disable(cfg->peripheral_id);
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break;
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default:
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LOG_ERR("The PMC clock type is not implemented.");
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return -ENODEV;
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}
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return 0;
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}
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static int atmel_sam_clock_control_get_rate(const struct device *dev,
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clock_control_subsys_t sys,
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uint32_t *rate)
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{
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ARG_UNUSED(dev);
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const struct atmel_sam_pmc_config *cfg = (const struct atmel_sam_pmc_config *)sys;
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if (cfg == NULL) {
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LOG_ERR("The PMC config can not be NULL.");
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return -ENXIO;
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}
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LOG_DBG("Type: %x, Id: %d", cfg->clock_type, cfg->peripheral_id);
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switch (cfg->clock_type) {
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case PMC_TYPE_PERIPHERAL:
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*rate = SOC_ATMEL_SAM_MCK_FREQ_HZ;
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break;
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default:
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LOG_ERR("The PMC clock type is not implemented.");
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return -ENODEV;
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}
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LOG_DBG("Rate: %d", *rate);
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return 0;
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}
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static enum clock_control_status
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atmel_sam_clock_control_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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const struct atmel_sam_pmc_config *cfg = (const struct atmel_sam_pmc_config *)sys;
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enum clock_control_status status;
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if (cfg == NULL) {
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LOG_ERR("The PMC config can not be NULL.");
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return -ENXIO;
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}
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LOG_DBG("Type: %x, Id: %d", cfg->clock_type, cfg->peripheral_id);
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switch (cfg->clock_type) {
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case PMC_TYPE_PERIPHERAL:
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status = soc_pmc_peripheral_is_enabled(cfg->peripheral_id) > 0
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? CLOCK_CONTROL_STATUS_ON
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: CLOCK_CONTROL_STATUS_OFF;
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break;
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default:
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LOG_ERR("The PMC clock type is not implemented.");
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return -ENODEV;
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}
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return status;
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}
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static struct clock_control_driver_api atmel_sam_clock_control_api = {
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.on = atmel_sam_clock_control_on,
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.off = atmel_sam_clock_control_off,
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.get_rate = atmel_sam_clock_control_get_rate,
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.get_status = atmel_sam_clock_control_get_status,
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};
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static int atmel_sam_clock_control_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, atmel_sam_clock_control_init,
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NULL,
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NULL,
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NULL,
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&atmel_sam_clock_control_api);

‎dts/arm/atmel/sam3x.dtsi

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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
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/ {
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aliases {
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};
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soc {
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pmc: pmc@400e0600 {
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compatible = "atmel,sam-pmc";
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reg = <0x400e0600 0x200>;
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interrupts = <5 0>;
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#clock-cells = <2>;
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status = "okay";
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};
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sram0: memory@20070000 {
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compatible = "mmio-sram";
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reg = <0x20070000 0x18000>;

‎dts/arm/atmel/sam4e.dtsi

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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
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/ {
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aliases {
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};
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soc {
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pmc: pmc@400e0400 {
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compatible = "atmel,sam-pmc";
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reg = <0x400e0400 0x200>;
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interrupts = <5 0>;
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#clock-cells = <2>;
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status = "okay";
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};

‎dts/arm/atmel/sam4l.dtsi

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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
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/ {
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chosen {
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};
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soc {
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pmc: pmc@400e0000 {
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compatible = "atmel,sam-pmc";
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reg = <0x400e0000 0x740>;
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interrupts = <22 0>;
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#clock-cells = <2>;
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status = "okay";
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};
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flashcalw: flash-controller@400a0000 {
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compatible = "atmel,sam4l-flashcalw-controller";
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reg = <0x400a0000 0x400>;

‎dts/arm/atmel/sam4s.dtsi

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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
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/ {
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aliases {
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};
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soc {
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pmc: pmc@400e0400 {
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compatible = "atmel,sam-pmc";
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reg = <0x400e0400 0x200>;
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interrupts = <5 0>;
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#clock-cells = <2>;
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status = "okay";
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};
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sram0: memory@20100000 {
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compatible = "mmio-sram";
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};

‎dts/arm/atmel/same70.dtsi

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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
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/ {
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aliases {
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};
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soc {
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pmc: pmc@400e0600 {
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compatible = "atmel,sam-pmc";
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reg = <0x400e0600 0x200>;
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interrupts = <5 0>;
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#clock-cells = <2>;
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status = "okay";
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};
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eefc: flash-controller@400e0c00 {
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compatible = "atmel,sam-flash-controller";
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reg = <0x400e0c00 0x200>;

‎dts/bindings/clock/atmel,sam-pmc.yaml

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# Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Atmel Power Management Controller (PMC)
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The Power Management Controller (PMC) optimizes power consumption by
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controlling all system and user peripheral clocks. The PMC enables/disables
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the clock inputs to many of the peripherals and the processor.
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To specify the clocks in a peripheral, the standard clocks property needs
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to be used, e.g.:
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uart: uart@xxx {
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...
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clocks = <&pmc PMC_TYPE_PERIPHERAL p-id>;
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...
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};
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In this example the clock-type was defined as PMC_TYPE_PERIPHERAL and the
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peripheral-id was defined as p-id. The p-id number should be consulted on
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datasheet, usually it is available at Product Mapping figure.
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NOTE: The predefined clock type cell is defined at
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include/zephyr/drivers/clock_clontrol/atmel_sam_pmc.h header file.
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The clock-type constants are:
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PMC_TYPE_CORE
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PMC_TYPE_SYSTEM
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PMC_TYPE_PERIPHERAL
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PMC_TYPE_GCK
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PMC_TYPE_PROGRAMMABLE
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compatible: "atmel,sam-pmc"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#clock-cells":
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const: 2
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description: |
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from common clock binding; shall be set to 2. The first entry is the type
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of the clock (core, system, peripheral or generated) and the second entry
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it's the peripheral identification index as provided by the datasheet.
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clock-cells:
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- clock-type
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- peripheral-id

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