intel_adsp: ace20_lnl: add initial ace 2.0 (LNL) board definition

This commit adds definition of ACE 2.0 Lunar Lake board.board.

Signed-off-by: Krzysztof Frydryk <Krzysztofx.Frydryk@intel.com>
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

Author: jxstelter

boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board

@@ -0,0 +1,8 @@
+# Xtensa board configuration
+
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config  BOARD_INTEL_ADSP_ACE20_LNL
+	bool "Intel ADSP ACE 2.0 Lunar Lake PCH"
+	depends on SOC_SERIES_INTEL_ACE

boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig

@@ -0,0 +1,10 @@
+# Copyright (c) 2022 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_INTEL_ADSP_ACE20_LNL
+
+config BOARD
+	default "intel_adsp_ace20_lnl"
+
+endif # BOARD_INTEL_ADSP_ACE20_LNL

boards/xtensa/intel_adsp_ace20_lnl/board.cmake

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(SUPPORTED_EMU_PLATFORMS acesim)
+
+board_set_rimage_target(lnl)

boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <intel/intel_adsp_ace20_lnl.dtsi>
+
+/ {
+	model = "intel_adsp_ace20_lnl";
+	compatible = "intel";
+
+	chosen {
+		zephyr,sram = &sram0;
+	};
+};

boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml

@@ -0,0 +1,14 @@
+identifier: intel_adsp_ace20_lnl
+name: ACE 2.0 LNL Audio DSP
+type: mcu
+arch: xtensa
+toolchain:
+  - xcc
+  - xt-clang
+supported:
+  - dma
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - mcumgr

boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_SOC_SERIES_INTEL_ACE=y
+CONFIG_SOC_INTEL_ACE20_LNL=y
+CONFIG_BOARD_INTEL_ADSP_ACE20_LNL=y
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_MM_DRV=y
+CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y

dts/bindings/dma/intel,adsp-hda.yaml

@@ -23,3 +23,6 @@ properties:
 
   "dma-copy-alignment":
     required: true
+
+dma-cells:
+  - channel